Optimizing direct threaded code by selective inlining

Piumarta, Ian; Riccardi, F

doi:10.1145/277650.277743

Cited by 61 publications

(23 citation statements)

References 5 publications

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“…For VMs running on desktop computers, multiple instructions are often combined dynamically. Piumarta et al [9] combined instructions dynamically and improved the performance of an interpreter with a RISC-style instruction set. In approaches such as JIT compilation, a VM has a machine code optimization mechanism because combining VM instructions creates extra room for optimization of the machine code implementing the combined instruction.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of Superinstructions for JavaScript Virtual Machine Generation System for Embedded Systems eJSTK

Nonaka

Ugawa

2019

Journal of Information Processing

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Embedded systems generally have a small amount of memory and slow CPUs. Therefore it is desirable to increase the speed of JavaScript virtual machines (VMs) without increasing memory footprint. In this research, we introduce superinstructions, combinations of constant load instructions and arithmetic, logical, and relational (ALR) instructions to increase execution speed. Introducing superinstructions increases the size of a VM. Thus, we designed superinstructions so that they would share their implementation code with the ALR instructions, from which they are made. Furthermore, we simplified their type-based dispatching code through specialization to the datatypes of their constant operands. We developed a VM generator that creates VMs that have superinstructions in accordance with this approach and a compiler that compiles JavaScript programs using them.

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of Superinstructions for JavaScript Virtual Machine Generation System for Embedded Systems eJSTK

Nonaka

Ugawa

2019

Journal of Information Processing

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“…Each micro-op is independently translated to a sequence of target binary code by the second translation phase. This second translation is performed by an automatically generated codegenerator, following a scheme similar to [24]. To enable the generation of this code-generator, each micro-op has a corresponding implementation written in a high-level programming language (C in this case).…”

Section: Dbt Targeting Ia With Qemumentioning

confidence: 99%

Harmonia

Ottoni

Hartin

Weaver

et al. 2011

Proceedings of the 8th ACM International Conference on Computing Frontiers

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Dynamic binary translation (DBT) has been widely used as a means to run applications created for one instruction-set architecture (ISA) on top of processors with a different ISA. Given the great amount of legacy software developed for PCs, based on the Intel R Architecture (IA) ISA, a lot of attention has been given to translating IA to other ISAs. The recent trends in industry for both smaller ultra-mobile PCs and more powerful embedded and mobile internet devices (e.g. smartphones) are blurring the frontiers between these distinct markets. As a result, this market convergence is creating great interest in DBT from ISAs that currently dominate the embedded and mobile-internet-device markets (e.g. ARM, MIPS, and PowerPC) to IA. This paper investigates the main challenges that arise when targeting IA in a DBT. We identify the two key issues in efficiently translating from other ISAs to IA: IA's small number of registers, and its condition-code handling mechanism. To address these issues, we propose a combination of software and hardware solutions. Although motivated by IA, these techniques are not IA-specific, and they can be applied to other architectures with similar limitations to make them better DBT-targets. We have prototyped these techniques in Harmonia, an ARM-to-IA DBT tool based on open-source QEMU. Our experiments show that Harmonia achieves an average of 55% (up to 164%) of the performance of highly optimized native binaries, and an average speedup of 2.2× on top of the baseline QEMU.

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“…Piumarta and Riccardi describe selective inlining [20] in which virtual instructions from the same basic block can be combined into a superinstruction at load time. The result is reduced dispatch overhead at run time in exchange for slightly higher load time overhead.…”

Section: Selective Inliningmentioning

confidence: 99%

Yeti

Zaleski

Brown

Stoodley

2007

Proceedings of the 3rd International Conference on Virtual Execution Environments

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The design of new programming languages benefits from interpretation, which can provide a simple initial implementation, flexibility to explore new language features, and portability to many platforms. The only downside is speed of execution, as there remains a large performance gap between even efficient interpreters and mixed-mode systems that include a just-in-time compiler (or JIT for short). Augmenting an interpreter with a JIT, however, is not a small task. Today, JITs used for Java TM are loosely-coupled with the interpreter, with callsites of methods being the only transition point between interpreted and native code. To compile whole methods, the JIT must duplicate a sizable amount of functionality already provided by the interpreter, leading to a "big bang" development effort before the JIT can be deployed. Instead, adding a JIT to an interpreter would be easier if it were possible to leverage the existing functionality.In earlier work we showed that packaging virtual instructions as lightweight callable routines is an efficient way to build an interpreter. In this paper we describe how callable bodies help our interpreter to efficiently identify and run traces. Our closely coupled dynamic compiler can fall back on the interpreter in various ways, permitting an incremental approach in which additional performance gains can be realized as it is extended in two dimensions: (i) generating code for more types of virtual instructions, and (ii) identifying larger compilation units. Currently, Yeti identifies straight line regions of code and traces, and generates non-optimized code for roughly 50 Java integer and object bytecodes. Yeti runs roughly twice as fast as a direct-threaded interpreter on SPECjvm98 benchmarks.

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Optimizing direct threaded code by selective inlining

Cited by 61 publications

References 5 publications

Design and Implementation of Superinstructions for JavaScript Virtual Machine Generation System for Embedded Systems eJSTK

Design and Implementation of Superinstructions for JavaScript Virtual Machine Generation System for Embedded Systems eJSTK

Harmonia

Yeti

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