Optimizing graph algorithms for improved cache performance

Park, Joon‐Sang; Penner, M.; Prasanna, Viktor K.

doi:10.1109/tpds.2004.44

Cited by 74 publications

(52 citation statements)

References 27 publications

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“…Challanges in parallel graph processing is discussed in [3] Our computations involve matrices and therefore some fast matrix multiplication algorithms such as [19][6] are also our area of concern. As CPU implementations have several limitations of performance so some cache optimization techniques and cache friendly implementations are given in [2]and [5] using recursion for dense graphs. In [10] to reduce TLB misses blocked data layout and mortan layout are given for FW.…”

Section: Problem Time Complexitymentioning

confidence: 99%

OpenCL Parallel Blocked Approach for Solving All Pairs Shortest Path Problem on GPU

Pandey¹,

Sharma²

2015

IJCA

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All-Pairs Shortest Path Problem (APSP) finds a large number of practical applications in real world. This paper presents a blocked parallel approach for APSP using an open standard framework OpenCL, which provides development environment for utilizing heterogeneous computing elements of computer system and to take advantage of massive parallel capabilities of multi-core processors such as graphics processing unit (GPU) and CPU. This blocked parallel approach exploits the local shared memory of GPU, thereby enhancing the overall performance. The proposed solution is for directed and dense graphs with no negative cycles and is based on blocked Floyd Warshall (FW) and Kleene"s algorithm. Like Floyd Warshall this approach is also in-place and therefore requires no extra memory.

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Section: Problem Time Complexitymentioning

confidence: 99%

OpenCL Parallel Blocked Approach for Solving All Pairs Shortest Path Problem on GPU

Pandey¹,

Sharma²

2015

IJCA

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“…Actual algorithms based on this proof are given by various researchers, with minor differences. Our decision to use the DC algorithm as our starting point is inspired by its demonstrated better cache reuse on CPUs [33], and its impressive performance attained on the many-core graphical processor units [11].…”

Section: Previous Workmentioning

confidence: 99%

“…The workflow of the DC-APSP algorithm is also pictured in Figure 2. The correctness of this algorithm has been proved by many researchers [4], [11], [33] using various methods. Edge weights can be arbitrary, including negative numbers, but we assume that the graph is free of negative cycles.…”

Section: Divide-and-conquer Apspmentioning

confidence: 99%

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Minimizing Communication in All-Pairs Shortest Paths

Solomonik¹,

Buluç²,

Demmel³

2013

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Abstract-We consider distributed memory algorithms for the all-pairs shortest paths (APSP) problem. Scaling the APSP problem to high concurrencies requires both minimizing inter-processor communication as well as maximizing temporal data locality. The 2.5D APSP algorithm, which is based on the divide-andconquer paradigm, satisfies both of these requirements: it can utilize any extra available memory to perform asymptotically less communication, and it is rich in semiring matrix multiplications, which have high temporal locality. We start by introducing a block-cyclic 2D (minimal memory) APSP algorithm. With a careful choice of block-size, this algorithm achieves known communication lower-bounds for latency and bandwidth. We extend this 2D block-cyclic algorithm to a 2.5D algorithm, which can use c extra copies of data to reduce the bandwidth cost by a factor of c 1/2 , compared to its 2D counterpart. However, the 2.5D algorithm increases the latency cost by c 1/2 . We provide a tighter lower bound on latency, which dictates that the latency overhead is necessary to reduce bandwidth along the critical path of execution. Our implementation achieves impressive performance and scaling to 24,576 cores of a Cray XE6 supercomputer by utilizing well-tuned intra-node kernels within the distributed memory algorithm.

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“…For the former, the optimization is performed during the compiling time through code transformation [10,8,9], array padding [1,14], or both of them [4], while for the later optimization is done directly within the source code via manually rewriting the program code using the same techniques [5,12]. In contrast to the compiler approach, the user-level optimization is more common due to its straight-forward manner.…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Spatial and Temporal Locality in Data Accesses

Tao¹,

Schloissnig²,

Karl³

2006

Computational Science – ICCS 2006

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Abstract. Cache optimization becomes increasingly important for achieving high computing performance, especially on current and future chip-multiprocessor (CMP) systems, which usually show a rather higher cache miss ratio than uniprocessors. For such optimization, information about the access locality is needed in order to help the user in the tasks of data allocation, data transformation, and code transformation which are often used to enhance the utilization of cached data towards a better cache hit rate.In this paper we demonstrate an analysis tool capable of detecting the spatial and temporal relationship between memory accesses and providing information, such as access pattern and access stride, which is required for applying some optimization techniques like address grouping, software prefetching, and code transformation. Based on the memory access trace generated by a code instrumentor, the analysis tool uses appropriate algorithms to detect repeated address sequences and the constant distance between accesses to the different elements of a data structure. This allows the users to pack data with spatial locality in the same cache block so that needed data can be loaded into the cache at the same time. In addition, the analysis tool computes the push back distance which shows how a cache miss can be avoided by reusing the data before replacement. This helps to reduce cache misses increasing therefore the temporal reusability of the working set.

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Optimizing graph algorithms for improved cache performance

Abstract: Abstract

Cited by 74 publications

References 27 publications

OpenCL Parallel Blocked Approach for Solving All Pairs Shortest Path Problem on GPU

OpenCL Parallel Blocked Approach for Solving All Pairs Shortest Path Problem on GPU

Minimizing Communication in All-Pairs Shortest Paths

Analysis of the Spatial and Temporal Locality in Data Accesses

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