Optimizing memory tests by analyzing defect coverage

Jee, A.; Colburn, Jonathon E.; Irrinki, V.S.; Puri, Munish

doi:10.1109/mtdt.2000.868611

Cited by 7 publications

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fault analysis is an important step in establishing detailed fault models for subsequent diagnostics and debugging of the semiconductor memory products. In [2,3], the authors simulate the SRAM circuits using different test algorithms based on the notion of weighted critical area (WCA). They also show the defect coverages and fault coverages of the test algorithms.…”

Section: Introductionmentioning

confidence: 99%

Defect oriented fault analysis for SRAM

Huang

Chou

2003

Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-0

View full text Add to dashboard Cite

Fault analysis is an important step in establishing detailed fault models for subsequent diagnostics and debugging of a semiconductor memory product. We have performed defect injection in the memory cell array of an industrial SRAM circuit and analyzed the faulty behavior with respect to each defect injected. We found that although some of the defects can be mapped to existing fault models, there are many defects that result in unmodeled faults. Moreover, a defect may exhibit a different faulty behavior at a different location in the cell array. The voltage and temperature parameters can also change the faulty behavior. The simulation results show that almost all open and short defects lead to stuck-at faults, transition faults, and data retention faults.

show abstract

Section: Introductionmentioning

confidence: 99%

Defect oriented fault analysis for SRAM

Huang

Chou

2003

Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-0

View full text Add to dashboard Cite

show abstract

“…They also show the analysis of the faulty memory behavior under different temperatures. In [7,8], the authors simulate the SRAM circuits using different test algorithms based on the notion of weighted critical area (WCA). They also show the defect coverage and fault coverage of the test algorithms.…”

Section: Introductionmentioning

confidence: 99%

SRAM delay fault modeling and test algorithm development

Huang¹,

Lai²,

Chou³

et al.

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

View full text Add to dashboard Cite

-With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of

show abstract

Testing Defects and Parametric Variations in RAMs

Sachdev

Gyvez

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

View full text Add to dashboard Cite

Optimizing memory tests by analyzing defect coverage

Cited by 7 publications

References 5 publications

Defect oriented fault analysis for SRAM

Defect oriented fault analysis for SRAM

SRAM delay fault modeling and test algorithm development

Testing Defects and Parametric Variations in RAMs

Contact Info

Product

Resources

About