Optimizing the DRAM refresh count for merged DRAM/logic LSIs

Ohsawa,; Kai, Kai; Murakami,

doi:10.1109/lpe.1998.708160

Cited by 22 publications

(40 citation statements)

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“…When the number of cycles between the previous refresh exceeds the pre-defined threshold, the line is refreshed. As reported in [12], the selective refresh saves 5%-60% of energy while the variable refresh can save up to 75%. Hwang, et al [13] proposed to apply array selfrefresh operation partially, i.e.…”

Section: Related Reseachmentioning

confidence: 85%

“…To [11] advocated reshaping input traffic to DRAM by making memory accesses less random and thus more controllable. To save DRAM refresh energy, Ohsawa, et al [12] used two schemes: a selective refresh with data allocation optimization and a variable period refreshing. The selective refresh scheme adds a valid bit to each memory row and only refreshes rows with valid bit set.…”

Section: Related Reseachmentioning

confidence: 99%

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Handheld System Energy Reduction by OS-Driven Refresh

Moshnyaga

Reinman

et al. 2006

Lecture Notes in Computer Science

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Abstract. Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy of memory system, which unlike others, lowers energy of refresh operation in DRAM. The approach is based on two key ideas: (1) DRAM-based flash cache that keeps dirty pages to reduce the number of accesses to flash memory; and (2) OS-controlled page allocation/aging to stop the refresh operations in banks, whose pages are clean and not accessed for a long time. Simulations show that by using this technique we can decrease the overall energy consumption of DRAM/flash memory on video applications by 8-26% while reducing the DRAM refresh energy by 59-74%.

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Section: Related Reseachmentioning

confidence: 85%

Section: Related Reseachmentioning

confidence: 99%

Handheld System Energy Reduction by OS-Driven Refresh

Moshnyaga

Reinman

et al. 2006

Lecture Notes in Computer Science

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show abstract

“…Error-Correcting Codes (ECC) have been also used to recover lost data due to extended refresh periods [31]. Finally, refresh can be skipped for data identified as useless [29]. Please refer to Section 5.3 for further information.…”

Section: Refresh Mechanismsmentioning

confidence: 99%

“…Some works fall into the second category [12] [30] [31] [29]. Liu et al [12] proposed a refresh mechanism, referred to as Retention-Aware Intelligent DRAM Refresh (RAIDR).…”

Section: Refresh Mechanisms In Off-chip Memoriesmentioning

confidence: 99%

Hybrid caches: design and data management

Valero¹

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“…Schemes for dynamically controlling the refresh period through a limited number of temperature or current sensors have been reported in [11,14]. The use of memory access history for reducing the number of refreshes to previously accessed rows has been proposed in [13]. The use of Error Correcting Codes (ECCs) to control the number of ertors below a required level while setting the refresh period to a higher value was reported for mass storage media in [9].…”

Section: Introductionmentioning

confidence: 99%

Block-based multi-period refresh for energy efficient dynamic memory

Kim

Papaefthymiou²

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

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Public Reporting burden for this collection of information is estimated to average 1 liour per response, including flie time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and conpleting and reviewing the collection of information. Send comment regarding this burden estimates or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302, and DRAMs are widely used In portable applications due to their high storage density. In standby mode their main source of power dissipation Is the refresh operation that periodically restores leaking charge In each cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage.In this paper we Investigate a novel scheme that relies on multiple refresh periods and small refresh blocks to reduce DRAM dissipation by decreasing the number of cells refreshed too often. Long periods are used to accommodate cells with small leakage. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Retention times are further extended by adding a swap cell to each refresh block.We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer Kand a distribution of data retention times, in O(KN^) steps our algorithm computes /< refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a possible implementation of our refresh scheme. In simulations with a 16Mb DRAM, block-based multi-rate refresh reduces standby dissipation by a multiplicative factor of 4 with area overhead below 6%. ABSTRACTDRAMs are widely used in portable applications due to their high storage density. In standby mode, their main source of power dissipation is the refresh operation that periodically restores leaking charge in each cell to its correct level. Conven

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Optimizing the DRAM refresh count for merged DRAM/logic LSIs

Cited by 22 publications

References 0 publications

Handheld System Energy Reduction by OS-Driven Refresh

Handheld System Energy Reduction by OS-Driven Refresh

Hybrid caches: design and data management

Block-based multi-period refresh for energy efficient dynamic memory

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