Optimum buffer circuits for driving long uniform lines

Dhar, Sanjay; Franklin, Mark A.

doi:10.1109/4.65707

Cited by 141 publications

(84 citation statements)

References 10 publications

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“…Buffer insertion and buffer sizing have been known for a long time to be effective techniques to reduce delay and have been extensively studied in the literature [1], [14], [19], [20], [23], [28]. As delay due to interconnect wire becomes more and more important, [13] demonstrated that wire sizing is also very effective in reducing interconnect delay.…”

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confidence: 99%

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Chu

Wong

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm modified active set method (MASM) to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn 2 ) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 0.92 s. In addition, we extend MASM to consider simultaneous buffer insertion, buffer sizing, and wire sizing. The resulting algorithm MASM-BS is again optimal and very efficient. For example, with six choices of buffer size and 10 choices of wire width, the optimal solution for a 15 000 m long wire can be found in 0.05 s. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used.

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confidence: 99%

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Chu

Wong

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…We break down the buffered wire design problem, which is a complex non-linear delay optimization problem as in [3], into three sub-problems (stages) : the prebuffer stage, : width of the wire Our wire architecture is depicted in Figure 4. For the post-buffer stage, we adopt the tapered configuration, starting with a minimum sized driver and find the optimal number of buffers (n post ) in this stage and their sizes ( Figure 5).…”

Section: Pre-mid-post Buffer Strategymentioning

confidence: 99%

“…A simple approach for the design of optimal buffers for driving long uniform lines, as shown by Dhar et al, would be to use buffers in a tapered configuration both at the source and the sink, and have equidistant buffer placement on the middle wire section [3]. But the wire delay thus obtained, is not purely a function of the wire length.…”

Section: Introductionmentioning

confidence: 99%

Interconnect delay minimization using a novel pre-mid-post buffer strategy

Prasad

Desai

16th International Conference on VLSI Design, 2003. Proceedings.

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We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suitable for high level design.

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“…Because hk is quasi concave in the quadrant of positive h and k, it is not possible to find an analytical solution to the first optimisation problem, which has to be solved numerically. The solution to the second optimisation problem is obtained by solving the Kuhn Tucker conditions [4] given in (8) through (12) where L, refer to the Lagrangian constants. The coefficients corresponding to case (a) have been used as the worst-case needs to be considered.…”

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confidence: 99%

On dynamic delay and repeater insertion

Tenhunen

Pamunuwa

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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In deep sub-micron technologies, as the wires are placed ever closer and signal rise and fall times go into the sub-nano second region, increased cross talk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. Here we show that in uniform coupled lines, the response for several important switching configurations has a dominant pole characteristic. This allows easy prediction for the average, worst-case and best-case delay of buffered lines. We show that the repeater numbering and sizing can be optimised to deal with cross-talk under different constraints to best match the application. Area and power issues are considered and all equations are checked against a dynamic circuit simulator (SPECTRE).

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Optimum buffer circuits for driving long uniform lines

Cited by 141 publications

References 10 publications

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Interconnect delay minimization using a novel pre-mid-post buffer strategy

On dynamic delay and repeater insertion

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