Origin of transient V&lt;inf&gt;th&lt;/inf&gt; shift after erase and its impact on 2D/3D structure charge trap flash memory cell operations

Park, Jong Kyung; Moon, Dong‐Il; Choi, Yang‐Kyu; Lee, Seok-Hee; Lee, Ki-Hong; Pyi, Seung-Ho; Cho, Byung Jin

doi:10.1109/iedm.2012.6478964

Cited by 10 publications

(11 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Two other recent works use a methodology similar to ours to characterize 3D NAND devices based on different 3D NAND flash memory cell technologies (i.e., 3D floating-gate cell and 3D vertical gate cell) [38,94,95], which are less common than the 3D charge trap NAND flash memory cell technology that we test in this paper. Other recent works [23,31,78,80,92] report several differences of 3D NAND flash memory from planar NAND flash memory. These differences include (1) smaller program variation at high P/E cycle counts [80], (2) smaller program interference [80], (3) layer-to-layer process variation [92], (4) early retention loss [23,31,78], and (5) retention interference [23].…”

Section: Related Workmentioning

confidence: 99%

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

View full text Add to dashboard Cite

Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory.In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell.Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

show abstract

Section: Related Workmentioning

confidence: 99%

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…Since scaling and design of 3D NAND are completely different from planar NAND, and with different implications on the memory reliability, new methodologies are [15] required. One of the problems of 3D NAND is the reduced cells density per single memory layer.…”

Section: Vertical Hole Design Limitationsmentioning

confidence: 99%

“…Waiting for the final V TH would significantly increase the total program/erase time and, of course, this is not acceptable. The transient threshold voltage shift after erase is due to hole re-distribution in the charge trap layer [15].…”

Section: Data Retentionmentioning

confidence: 99%

See 1 more Smart Citation

Reliability of 3D NAND Flash Memories

2016

View full text Add to dashboard Cite

In this chapter the main reliability mechanisms affecting 3D NAND memories will be addressed, providing a comparison between 3D FG and 3D CT devices in terms of reliability and expected performances. Starting from an analysis of basic reliability issues related to both physical and architectural aspects affecting NAND memories, the specific physical mechanisms impacting the reliability of 2D CT NAND will be addressed. Then, a review of the main problems experimentally observed in different 3D CT cell concepts is reported. Finally, 3D FG memory concept is briefly introduced in order to understand the related reliability implications, and a comparison between 3D CT and 3D FG arrays is provided in terms of reliability and expected performances

show abstract

“…More recently, increasing attention has been paid to the reliability issues of charge trapping memory (CTM). A lot of effort is dedicated to investigate the retention reliability issues caused by formation of vertical charge dipole [2], charge trapping into defects in high-k blocking oxide [3][4] and trapped charge redistribution after erasing [5], whereas much less research is aiming at discovering the performance of charge trapping memory after programming/erasing (P/E) cycling. However, the modeling of trap generation at Si/SiO 2 interface and inside tunneling oxide and their effects is of great importance to understand cyclingrelated degradation phenomenon of CTM.…”

Section: Introductionmentioning

confidence: 99%

Simulation on endurance characteristic of charge trapping memory

Lun

Wang

Zeng

et al. 2013

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

View full text Add to dashboard Cite

Fig.1. Schematic of the studied charge trapping device in this work. Fig.2. Mechanisms included to investigate (a) generation of Si/SiO2 interface trapped charge and (b) oxide trapped charge.Abstract-A comprehensive simulation method for endurance reliability issues in charge trapping memory is developed. For this purpose, a practical algorithm is carefully designed to investigate the cycling performance of charge trapping memory. The models that account for the generation of substrate/tunneling oxide interface trapped charge and oxide trapped charge are incorporated into the simulation. The influence of these models on flat-band voltage evolution under programing/erasing cycling is investigated in detail, thus providing insight into the mechanism of the endurance issues in charge trapping memory.

show abstract

Origin of transient V<inf>th</inf> shift after erase and its impact on 2D/3D structure charge trap flash memory cell operations

Cited by 10 publications

References 7 publications

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Reliability of 3D NAND Flash Memories

Simulation on endurance characteristic of charge trapping memory

Contact Info

Product

Resources

About