Overlap junctions for superconducting quantum electronics and amplifiers

Bal, Mustafa; Long, Junling; Zhao, Ruichen; Wang, H.; Park, Sungoh; McRae, Corey Rae; Zhao, Tianyu; Lake, Russell; Monarkha, V. Yu.; Simbierowicz, Slawomir; Frolov, Daniil; Pilipenko, Roman; Zorzetti, Silvia; Romanenko, Alexander; Liu, Chuan-Hong; McDermott, Robert; Pappas, David P.

doi:10.1063/5.0048621

Cited by 4 publications

(2 citation statements)

References 20 publications

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“…Several alternatives to double-angle evaporated junctions exist, including finMET 31 , trilayer 30,32 , and overlap [33][34][35][36][37] Josephson junctions. These are compatible with manufacturable CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms

et al. 2022

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As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the-art superconducting qubits are generally incompatible with modern-day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling—the critical step during junction fabrication—and a subtractive-etch process nevertheless result in qubits with average qubit energy relaxation times T1 reaching 70 µs, with maximum values exceeding 100 µs. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process, therefore, heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.

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Section: Introductionmentioning

confidence: 99%

Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms

et al. 2022

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“…However, this method has a poor Dolan bridge stability and narrow process window and, therefore, precise control of the fabrication operations is required. The recently developed subtractive methods for junction fabrication have shown promising results [25][26][27][28] . However, these methods require additional process steps with an extremely careful control of interfaces, which makes fabrication significantly more complicated.…”

Section: Methodsmentioning

confidence: 99%

Improving Josephson junction reproducibility for superconducting quantum circuits: junction area fluctuation

Pishchimova

Smirnov

Ezenkova

et al. 2023

Sci Rep

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Josephson superconducting qubits and parametric amplifiers are prominent examples of superconducting quantum circuits that have shown rapid progress in recent years. As such devices become more complex, the requirements for reproducibility of their electrical properties across a chip are being tightened. Critical current of the Josephson junction Ic is the essential electrical parameter in a chip. So, its variation is to be minimized. According to the Ambegaokar–Baratoff formula, critical current is related to normal-state resistance, which can be measured at room temperature. In this study, we focused on the dominant source of non-uniformity for the Josephson junction critical current–junction area variation. We optimized Josephson junction fabrication process and demonstrated resistance variation of 9.8–4.4% and 4.8–2.3% across 22 × 22 mm2 and 5 × 10 mm2 chip areas, respectively. For a wide range of junction areas from 0.008 to 0.12 μm2, we ensure a small linewidth standard deviation of 4 nm measured over 4500 junctions with linear dimensions from 80 to 680 nm. We found that the dominate source of junction area variation limiting $${\mathrm{I}}_{\mathrm{c}}$$ I c reproducibility is the imperfection of the evaporation system. The developed fabrication process was tested on superconducting highly coherent transmon qubits (T1 > 100 μs) and a nonlinear asymmetric inductive element parametric amplifier.

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