Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Ker, Ming‐Dou; Chang, Wei‐Jen

doi:10.1016/j.microrel.2006.03.012

Cited by 6 publications

(1 citation statement)

References 21 publications

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“…The layouts of these ESD devices differ discernibly. The pad ESD structures are the most critical and are laid out completely in accordance with the special ESD-optimized process rules [24,25] based on or similar to various published ESD-focused layout optimization methods for MOS transistors [26][27][28] and other devices [27,29]. The local mini structures follow the most critical of these rules.…”

Section: Overvoltage and Esd Safety Devicesmentioning

confidence: 99%

Influence of Modifications Related to Safe Operating Area Demands on Operation of a Specialized Medium/High-Voltage Unity-Gain Buffer

Jankowski

2021

Energies

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This paper presents safety-related modifications to the improved high-voltage unity-gain buffer and their impact on the operation quality of this circuit. The analyzed buffer architecture combines the virtues of source and gate followers. It provides high input impedance to the gate follower and voltage gain precision to the source follower while retaining a very simple structure and an extremely short signal path. These properties enable its various applications, e.g., as an interconnection of voltage and current mode function blocks in signal paths of medium- and high-voltage integrated circuits. The scrutinized buffer consists of MOS devices with different maximum interterminal voltages, which results in the necessity of enhancing its architecture with a set of safety devices to ensure non-destructive power-up, normal operation, and power-down phases of the buffer operation. The consequences of the implemented safety changes vs. the influence of the physical implementation process on the buffer operation capabilities are presented in comparison to its ancestral source and gate followers. The results show that the analyzed buffer retains the best signal processing quality among the compared buffer structures after the complete physical implementation process.

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