ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Ker, Ming‐Dou; Chang, Wei‐Jen

doi:10.1109/ted.2008.920972

Cited by 28 publications

(4 citation statements)

References 25 publications

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“…In this paper, the ESD protection schemes and high-voltagetolerant ESD clamp circuits designed to protect the mixedvoltage I/O interfaces against ESD stresses without suffering the gate-oxide reliability issue are presented [15], [16]. With consideration of gate-leakage issue, a new high-voltagetolerant low-leakage ESD clamp circuit has been designed and successfully verified in the nanoscale CMOS processes with only thin gate-oxide devices [17].…”

Section: * This Work Was Supported By Ministry Of Economic Affairs Tmentioning

confidence: 99%

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Ker

Wang

2009

2009 IEEE Custom Integrated Circuits Conference

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Electrostatic discharge (ESD) protection for mixedvoltage I/O interfaces has been one of the major challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. Moreover, the gate leakage current across thin gateoxide devices has serious degradation on circuit performance while circuits implementing in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O buffers should meet the gate-oxide reliability constraints and be designed with consideration of gate leakage current. This paper presents the effective ESD protection scheme with circuit solutions to protect the mixed-voltage I/O buffers in nanoscale CMOS processes against ESD stresses. The proposed ESD protection scheme and the specific ESD clamp circuits with low standby leakage current have been successfully verified in nanoscale CMOS processes. Effective on-chip ESD protection scheme should be early planed and started in the beginning phase of chip design in order to achieve good enough ESD robustness for IC products.

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Section: * This Work Was Supported By Ministry Of Economic Affairs Tmentioning

confidence: 99%

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Ker

Wang

2009

2009 IEEE Custom Integrated Circuits Conference

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“…[1][2][3] The phenomenon of ESD leads to permanent device damage associated with the breakdowns of junctions, metal interconnects and dielectrics, caused by high current transients and high voltage overstress. Nowadays, IC dimensions have been continuously scaled down to realize higher packing density, faster operation speed and lower power dissipation.…”

Section: Introductionmentioning

confidence: 99%

High Performance ESD/Surge Protection Capability of Bidirectional Flip Chip Transient Voltage Suppression Diodes

Pharkphoumy¹,

Khurelbaatar²,

Janardhanam³

et al. 2016

Transactions on Electrical and Electronic Materials

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We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n-epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

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“…Ideal ESD power clamp should have low trigger on voltage, high immunity for latch up and enough margin for reliability under high voltage operation. Several proposals based on substrate triggered snapback scheme were proposed [3], [4], but these clamps could be false triggered in latch up event and didn't address on the performance of life time tests.…”

Section: Introductionmentioning

confidence: 99%

Gate-driven 3.3V ESD clamp using 1.8V transistors

Wang

Chen

Huang

et al. 2011

2011 IEEE International Conference on IC Design &Amp; Technology

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A new gate driven 3.3V ESD clamp circuit using 1.8V transistor is proposed. This new clamp circuit is suitable for ESD protection of legacy 3.3V I/O interface circuit in SOC chips which use only 1.8V I/O transistors. This clamp along with 3.3V I/O have been demonstrated in 40nm 1.8V process. Life-time test can pass 1000-hours prolonged operation. ESD/Latch-up can pass HBM 3KV, MM 300V, and +/-200mA current triggering and 4.95V (1.5 x VDD) over-voltage test. Index Terms-gate-driven, gate oxide over-stress, human-body model (HBM), machine model (MM)

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ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Cited by 28 publications

References 25 publications

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

High Performance ESD/Surge Protection Capability of Bidirectional Flip Chip Transient Voltage Suppression Diodes

Gate-driven 3.3V ESD clamp using 1.8V transistors

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