Oxide-based RRAM models for circuit designers: A comparative analysis

Hajri, Basma; Mansour, Mohammad M.; Chehab, Ali; Aziza, Hassen

doi:10.1109/dtis.2017.7930176

Cited by 20 publications

(13 citation statements)

References 19 publications

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“…V Cell is the voltage across the cell and I Cell the current through the cell. A good agreement with experimental data is obtained with a ±5% standard deviation on parameters α and Lx of the model, where Lx is the OxRAM oxide thickness and α is the transfer coefficients (ranging between 0 and 1) [22].…”

Section: Mlc Design Schemesupporting

confidence: 73%

“…In addition to the large HRS window available for MLC, targeting the HRS, instead of the LRS domain, will result in a significant reduction in energy during the READ operations following the programming operations. For memory array simulations, a compact OxRAM model [21,22] calibrated on measurements proposed in Section 2 is used. The model accurately reproduces the stochastic switching nature of OxRAM cells.…”

Section: Oxram Modelmentioning

confidence: 99%

“…At the design level, a write termination circuit is used to constantly sense the RST current and stop the programming pulse when the preferred RST current is reached, resulting in well-defined HRS resistances. For memory array simulations, a compact OxRAM model [21,22] calibrated on measurements proposed in Section 2 is used. The model accurately reproduces the stochastic switching nature of OxRAM cells.…”

Section: Mlc Design Schemementioning

confidence: 99%

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Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

et al. 2021

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RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation without the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implemented based on a strict control of the cell programming current of 1T-1R HfO2-based RRAM cells. From a design standpoint, a self-adaptive write termination circuit is proposed to control the RESET operation and provide an accurate tuning of the analog resistance value of each cell of a memory array. The different resistance levels are obtained by varying the compliance current in the RESET direction. Impact of variability on resistance margins is simulated and analyzed quantitatively at the circuit level to guarantee the robustness of the proposed MLC scheme. The minimal resistance margin reported between two consecutive states is 2.1 kΩ along with an average energy consumption and latency of 25 pJ/cell and 1.65 μs, respectively.

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Section: Mlc Design Schemesupporting

confidence: 73%

Section: Oxram Modelmentioning

confidence: 99%

Section: Mlc Design Schemementioning

confidence: 99%

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Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

et al. 2021

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“…A single RRAM device (Figure 7) is simulated using each model. The transient I-V characteristics of the different simulated models using this configuration have been published in our previous work [30]; and the results are explained in Section V.…”

Section: B 1r Configurationmentioning

confidence: 99%

RRAM Device Models: A Comparative Analysis With Experimental Validation

Hajri¹,

Aziza²,

Mansour³

et al. 2019

IEEE Access

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Resistive Random Access Memories (RRAM) have recently shown outstanding characteristics such as high-scalability, high-speed, high-density, and low-energy operation. A simple and accurate model is crucial for rapid design and verification when using RRAM devices at the circuit level. The appropriate model selection gives insight into the behavior of RRAM as well as the efficient use of its unique properties. This work intends to guide the circuit designers in selecting the most appropriate RRAM model for their applications. We introduce a complete set of evaluation criteria for memristor models: type of model, type of switching, genericity, complexity, compatibility with actual physical switching mechanisms, linearity, symmetry, voltage/current control, hard set/soft reset, support electroforming, support for high programming signal frequencies, existence of a threshold, voltage level, timing dependence, temperature dependence and variability. This study compares the main existing RRAM models and summarizes the results in a table showing the main features and limitations of each model. Through extensive simulations and comparisons with experimental data, we provide an analysis and a validation of the reviewed models within the same simulation environment, ranging from individual elementary cells to large memory arrays. Furthermore, we provide a single and unique Verilog-A code integrating all the compared models.

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“…The OxRAM model used for simulations is a compact model calibrated on silicon well suited to simultaneously describe SET and RESET operations [27]. 4 Non-volatile SRAM…”

Section: T1r Oxram Cell Simulationmentioning

confidence: 99%

Non-volatile SRAM memory cells based on ReRAM technology

et al. 2020

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Static Random-Access Memories (SRAMs) are very common in today's chip industry due to their speed and power consumption but are classified as volatile memories. Non-volatile SRAMs (nvSRAMs) combine SRAM features with nonvolatility. This combination has the advantage to retain data after power off or in the case of power failure, enabling energy-efficient and reliable systems under frequent power-off conditions. In this work, several nvSRAMs architectures based on Oxide Random-Access Memory (OxRAM) technology are presented and compared. OxRAMs are non-volatile memories considered as a subset of Resistive RAM (ReRAM) technology.

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Oxide-based RRAM models for circuit designers: A comparative analysis

Cited by 20 publications

References 19 publications

Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

RRAM Device Models: A Comparative Analysis With Experimental Validation

Non-volatile SRAM memory cells based on ReRAM technology

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