Resistive Random Access Memories (RRAM) have recently shown outstanding characteristics such as high-scalability, high-speed, high-density, and low-energy operation. A simple and accurate model is crucial for rapid design and verification when using RRAM devices at the circuit level. The appropriate model selection gives insight into the behavior of RRAM as well as the efficient use of its unique properties. This work intends to guide the circuit designers in selecting the most appropriate RRAM model for their applications. We introduce a complete set of evaluation criteria for memristor models: type of model, type of switching, genericity, complexity, compatibility with actual physical switching mechanisms, linearity, symmetry, voltage/current control, hard set/soft reset, support electroforming, support for high programming signal frequencies, existence of a threshold, voltage level, timing dependence, temperature dependence and variability. This study compares the main existing RRAM models and summarizes the results in a table showing the main features and limitations of each model. Through extensive simulations and comparisons with experimental data, we provide an analysis and a validation of the reviewed models within the same simulation environment, ranging from individual elementary cells to large memory arrays. Furthermore, we provide a single and unique Verilog-A code integrating all the compared models.

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Common problems with Oxide-based Resistive RAM are related to high variability in operating conditions and high programming currents during FORMING, SET and RESET operations. Although research has taken steps to resolve these issues, variability combined with high programming currents remains an important characteristic for RRAMs. In a conventional write scheme with fixed duration and amplitude, the programming current is not controlled, which degrades the cell performance (power consumption and variability) due to over-programming. In this paper, a self-adaptive write driver is proposed to control the write current. A feedback mechanism based on current comparison is used to switch off the write stimulus as soon as the preferred write current is reached. Compared to conventional write schemes, in the proposed write-assist circuit, the write energy per bit is reduced by 27% and the standard deviation of post-FORMING distributions is reduced by 57%.

Recently, memristors received considerable attention in various applications. Even some of the main drawbacks of resistive memory devices (RRAM), such as variability, have become attractive features for hardware security in the form of a Physically Unclonable Function (PUF). Although several RRAM-based PUFs have appeared in the literature, they still suffer from some issues related to reliability, reconfigurability, and extensive integration cost. This paper presents a novel lightweight reconfigurable RRAM-based PUF (LRR-PUF) wherein multiple RRAM cells, connected to the same bit line and same transistor (1T4R), are used to generate a single bit response. The pulse programming method used is also innovative: 1) it allows for a power-efficient implementation, and 2) it exploits variations in the number of pulses needed to switch the RRAM cell as the primary entropy source of the PUF. The main feature of the proposed PUF is its integration with any RRAM architecture at almost no additional cost. Through extensive simulations, including the impact of temperature and voltage variations along with statistical characterization, we demonstrate that the LRR-PUF exhibits such attractive properties that are lacking or poorly achieved in other previously proposed RRAM based PUFs, including high reliability (almost 100%), which is critical for cryptographic key generation, reconfigurability, uniqueness, cost, and efficiency. Furthermore, the design successfully passes relevant NIST tests for randomness.

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