A lightweight write-assist scheme for reduced RRAM variability and power

Aziza, Hassen; Hajri, Basma; Mansour, Mohammad M.; Chehab, Ali; Perez, A.

doi:10.1016/j.microrel.2018.07.065

Cited by 6 publications

(5 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Nevertheless, the RTH value (or equivalently the ITOT value) has to be tuned for each random number generation step. Methods have been proposed in literature and can be adapted in our technology [4,36,37], based on a current comparator we proposed in a previous work [38]. We will discuss in section IV.E the robustness of our methodology and the real need to track the right RTH value during the lifetime of the TRNG circuit.…”

Section: Choice Of the Threshold Resistance Rthmentioning

confidence: 99%

True Random Number Generator Integration in a Resistive RAM Memory Array Using Input Current Limitation

Aziza

Postel-Pellerin

Bazzi

et al. 2020

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

A novel True Random Number Generator circuit fabricated in a 130nm HfO2-based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, all the cells of the memory array are addressed at the same time while the current provided to the circuit is limited to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, other cells are slightly programmed to reach an intermediate resistance state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed twelve NIST tests out of fifteen. Compared to state-of-the-art resistive RAM-based true random number generators, our proposed methodology is the first one to leverage on programming current limitation at a memory array level.

show abstract

Section: Choice Of the Threshold Resistance Rthmentioning

confidence: 99%

True Random Number Generator Integration in a Resistive RAM Memory Array Using Input Current Limitation

Aziza

Postel-Pellerin

Bazzi

et al. 2020

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

show abstract

“…In contrast, for the SET operation, only 3 transistors are needed. In [8], only the FMG operation is addressed along with a pulse programming approach. Authors achieved a 27% energy reduction along with a 57% reduction of the standard deviation of post-FMG distributions.…”

Section: Comparison With State-of-the-artmentioning

confidence: 99%

An Energy-Efficient Current-Controlled Write and Read Scheme for Resistive RAMs (RRAMs)

et al. 2020

Self Cite

View full text Add to dashboard Cite

Energy efficiency remains one of the main factors for improving the key performance markers of RRAMs to support IoT edge devices. This paper proposes a simple and feasible low power design scheme which can be used as a powerful tool for energy reduction in RRAM circuits. The design scheme is exclusively based on current control during write and read operations and ensures that write operations are completed without wasted energy. Self-adaptive write termination circuits are proposed to control the RRAM current during FORMING, RESET and SET operations. The termination circuits sense the programming current and stop the write pulse as soon as a preferred programming current is reached. Simulation results demonstrate that an appropriate choice of the programming currents can help obtain 4.1X improvement in FORMING, 9.1X improvement in SET and 1.12X improvement in RESET energy. Also, the possibility to have a tight control over the RESET resistance is demonstrated. READ energy optimization is also covered by leveraging on a differential sense amplifier offering a programmable current reference. Finally, an optimal trade-off between energy consumption during SET/RESET operations and an acceptable read margin is established according to the final application requirements. INDEX TERMSResistive RAM (ReRAM), RRAM, OxRAM, energy optimization, write termination, programming current, read current.

show abstract

“…3 presents the general scheme of the suggested LRR-PUF operation. When a challenge is applied, the selected RRAM cells are SET progressively (1) via pulse programming until they reach a certain reference current detected by a sense amplifier (2) during a READ operation [14]. A multi-bit counter (3) is then used to count the number of pulses required to SET the selected RRAM cells, and finally, the different outputs of the counter are XORed (4) to generate a single response.…”

Section: A One Cell Lrr-puf Architecturementioning

confidence: 99%

A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications

Hajri

Mansour

Chehab

et al. 2020

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

View full text Add to dashboard Cite

Recently, memristors received considerable attention in various applications. Even some of the main drawbacks of resistive memory devices (RRAM), such as variability, have become attractive features for hardware security in the form of a Physically Unclonable Function (PUF). Although several RRAM-based PUFs have appeared in the literature, they still suffer from some issues related to reliability, reconfigurability, and extensive integration cost. This paper presents a novel lightweight reconfigurable RRAM-based PUF (LRR-PUF) wherein multiple RRAM cells, connected to the same bit line and same transistor (1T4R), are used to generate a single bit response. The pulse programming method used is also innovative: 1) it allows for a power-efficient implementation, and 2) it exploits variations in the number of pulses needed to switch the RRAM cell as the primary entropy source of the PUF. The main feature of the proposed PUF is its integration with any RRAM architecture at almost no additional cost. Through extensive simulations, including the impact of temperature and voltage variations along with statistical characterization, we demonstrate that the LRR-PUF exhibits such attractive properties that are lacking or poorly achieved in other previously proposed RRAM based PUFs, including high reliability (almost 100%), which is critical for cryptographic key generation, reconfigurability, uniqueness, cost, and efficiency. Furthermore, the design successfully passes relevant NIST tests for randomness.

show abstract

A lightweight write-assist scheme for reduced RRAM variability and power

Cited by 6 publications

References 11 publications

True Random Number Generator Integration in a Resistive RAM Memory Array Using Input Current Limitation

True Random Number Generator Integration in a Resistive RAM Memory Array Using Input Current Limitation

An Energy-Efficient Current-Controlled Write and Read Scheme for Resistive RAMs (RRAMs)

A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications

Contact Info

Product

Resources

About