However, the high cost of SiC wafers brings an insurmountable barrier toward the batch production. Mature transfer techniques are also under development for the application in microelectronics. Additionally, the number of layers seems not well controlled, resulting in an unsatisfied nonuniformity over the entire 2-in. wafer. [35] Raman mapping for the 2D peak indicates the variation of layer thickness and strain (Figure 2b). [35] Upon correcting the peak shift caused by the strain, the map in Figure 2c ultimately shows that the graphene epitaxially grown on SiC is dominantly 1-2 layers. [35] Meanwhile, reduced graphene oxide (rGO) could also fulfill wafer-scale films affording high uniformity. [33,[36][37][38] Recently, Juvaid et al. reported the synthesis rGO films on target substrates by pulsed laser deposition (PLD), as depicted in Figure 2d. [33] A 4-in. wafer can be attained (Figure 2e), which is featured by smooth surface, high transparency, and excellent uniformity (evaluated by Raman spectroscopy in Figure 2f). [33] Despite these advances, the process of chemical oxidation introduces a large number of defects in the crystalline structure of rGO, resulting in marked decline in the electrical and thermal properties. [12] CVD is found to be the most widely used technique in semiconductor industry to synthesize thin films, which, in particular, is able to produce large-area graphene films on metallic or insulating substrates in controllable fashions. [39][40][41][42][43] In a typical CVD process for graphene synthesis, carbon gaseous precursor flows through the hightemperature reaction zone and generates active reaction species for subsequent nucleation and growth of graphene Figure 1. Various types of devices based on wafer-scale graphene films. The central panel: photos of wafer-scale graphene devices.Reproduced with permission. [16] Copyright 2010, Science. Reproduced with permission. [15] Copyright 2020, Springer Nature. Reproduced with permission. [17] Copyright 2019, Wiley-VCH. Reproduced with permission. [18] Copyright 2019, Wiley-VCH. a) Schematic illustration of the transfer process of CVD graphene onto a single CMOS die containing a read-out circuit of the image sensor. Reproduced with permission. [19] Copyright 2017, Springer Nature. b) 3D schematic illustration of a graphene-based waveguide-integrated electro-absorption modulator. Reproduced with permission. [20] Copyright 2011, Springer Nature. c) Schematic of a dual-gate bilayer graphene transistor device. Reproduced with permission. [21] Copyright 2010, American Chemical Society. d) Tilted view scanning electron microscopy image of a graphene receiver integrated circuit, showing the integration architecture of key components including graphene field effect transistor (GFET). Reproduced with permission. [22] Copyright 2014, Springer Nature. e) Schematic of device architectures proposed in resistive random access memory technology based on graphene and related materials. Reproduced with permission. [23] Copyright 2017, Wiley-VCH. f ) Schematic re...