P‐5.3: Design of Amorphous Silicon Thin‐Film Transistor Gate Driver Circuit with High Reliability and Narrow Border for Middle Size Liquid Crystal Display

Abstract

In this paper, an integrated hydrogenated amorphous silicon (a‐Si: H) thin‐film transistor (TFT) gate driver circuit design with high reliability and the narrow border for middle size liquid crystal display is demonstrated. The circuit design with two sets of the low‐level holding unit can increase the reliability and suppress the threshold voltage (Vth) shift of TFT in the circuit. In addition, the low‐level holding unit is floating in the Q node pre‐charge period, ensuring that the low‐level holding unit can be efficiently turn off during the selected stage working. As a result, the circuit is very stable even at the TFT Vth shift of 3V in the high‐temperature operation.

Highly reliable a‐Si:H gate driver on array with complementary double‐sided noise‐eliminating and dual voltage levels for TFT‐LCD applications

“…Especially, gate driver on array (GOA) using a-Si:H TFTs integrated on glass substrates possesses a variety of advantages, including low fabrication costs and the reductions of external driver ICs and border processes. [1][2][3][4][5][6][7][8][9][10][11] However, there are several problems for the GOA using a-Si:H TFT, such as low effect-field mobility, long-term stress degradation, and high parasitic capacitance.…”

P‐4.4: Path Planning Analysis of Pad Bending Process for the Full Screen OLED Panel

“…[1][2][3] In order to achieve a full screen for the OLED (organic light emitting diode) panels, the top and side parts can achieve a narrow margin with the help of shape design and circuit design. [4][5][6] While on the bottom part of the panel, there is a pad connected with the integrated circuit chip. In order to achieve a narrow margin, the pad has to be folded to the back of the panel.…”

High‐reliability gate driver on array using noise sharing of precharging node for thin film transistor–liquid crystal display application

“…Take previous studies, [15][16][17][18][19][20][21] for example. The former structure uses the DC voltage collocated with diode-connecting TFT, 15,21 and the latter structure uses coupling signal of driving clock [16][17][18][19][20] to charge the low-level holding TFTs like T7, T8, T14, and T15 for preventing the noise. In Hu et al, 15 the bipolar pulses and two replicated noise-free blocks are used to reach full-time noise free and F I G U R E 1 Gate driver with parallel bipolar pulses noise-free block 15…”

“…Furthermore, decreasing the fabrication cost is one of the most important demand for the display market. As a result, the integrated gate driver 1–21 based on amorphous silicon thin‐film transistors (a‐Si TFTs) has become a main stream in generation of display nowadays because it provides many advantages including reduction in the cost by eliminating external driver ICs and bonding connections, improvement on compactness and reliability, and simplification of data driver configuration.…”

“…The structure of noise‐free blocks are divided into two types: diode‐connecting and clock‐coupling. Take previous studies, 15–21 for example. The former structure uses the DC voltage collocated with diode‐connecting TFT, 15,21 and the latter structure uses coupling signal of driving clock 16–20 to charge the low‐level holding TFTs like T7, T8, T14, and T15 for preventing the noise.…”