Electrical Performance of Electronic Packaging,
DOI: 10.1109/epep.2002.1057924
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Package and chip design optimization for mid-frequency power distribution decoupling

Abstract: In this paper the mid-frequency power supply noise has been studied for a complex, next generation computer system by simulations of the complete module and board power distribution system. An MCM-D and MCM-C design and the effectiveness of on-chip and discrete on-module decoupling capacitors have been compared. The impact of delta-I ramping over several cycles and the impact of the continuous background switching and on-chip leakage have been analyzed. Conclusions are presented to optimize the chip and packag… Show more

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Cited by 4 publications
(2 citation statements)
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“…PU7 (Figure 2) has the largest mid-frequency noise because this chip has module capacitors at two chip edges only, which increases the loop inductance [12]. The module capacitor locations are clearly indicated by the low peak noise in Figure 7.…”
Section: Near Endmentioning
confidence: 92%
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“…PU7 (Figure 2) has the largest mid-frequency noise because this chip has module capacitors at two chip edges only, which increases the loop inductance [12]. The module capacitor locations are clearly indicated by the low peak noise in Figure 7.…”
Section: Near Endmentioning
confidence: 92%
“…The voltage change exhibits a damped mid-frequency oscillation with 42 MHz and 65-mV peak, which is just within the specified range for the mid-frequency noise. A detailed sensitivity analysis [12] has shown that the noise peak is determined for each chip on this MCM by the chip ⌬I, the on-chip capacitance and the inductance loop from Change of supply voltage on the corner PU chip (PU7) after a 20% change of on-chip switching activity at time zero (SPEED2000 simulation). Table 4 Total coupled noise as distributed from all adjacent signal lines.…”
Section: Power Integritymentioning
confidence: 99%