Package Technology to Address the Memory Bandwidth Challenge for Terascale Computing

Abstract

Tera-scale computing stresses the platform architecture with memory bandwidth being a likely bottleneck to processor performance that presents unique challenges to CPU packaging. This paper describes the evolution in packaging technology with each processor generation to meet increasing memory bandwidth needs and the revolution in package technology required for tera-scale computing needs. The scope and focus of the paper are primarily design and electrical performance challenges. We discuss a potential roadmap of transitions in package architecture and technology that evolves from today's offpackage memory scenario to increasingly complex onpackage integrated memory architectures. An overall treatment of memory hierarchy, including off-die memory approaches, is not within the scope of this paper, but relevant to the overall challenge of enabling higher bandwidth. Again, the focus of this paper is on the CPU package itself. In this context, we discuss the memory bandwidth limitations, technology challenges, and tradeoffs of each package architecture.

Understanding the design trade-offs among current multicore systems for numerical computations

“…The systems also differ in their deliverable memory bandwidth [22]. In terms of peak aggregate bandwidth, the 2P Harpertown system can deliver 21.4 GB/s, the 4P Barcelona system supports 42.8 GB/s, the QS20 and QS22 blades support 51.2 GB/s for main memory access.…”

Insights on memory controller scaling in multi-core embedded systems

“…Figure 2b illustrates (b) how significant are pin-count magnitudes in current systems. It also shows how bandwidth is restricted in terms of number of MCs and pins in Intel systems according to Polka [26]. Furthermore, it shows larger MC-and pincounts of GPUs such as NVIDIA GPU GT200 (8 MCs, 2500 pins) as well as embedded Tilera Tile 64 (4 MCs, 1500 pins).…”

Heterogeneous 2.5D integration on through silicon interposer

“…To meet Tera-scale computing needs and to reduce power consumption for next generation information devices, short and high density interconnections between high-capacity memory chips and microprocessor unit are required. [55][56][57] In order to achieve interconnections with low resistance, most frequently solder micro-bumps are made up of Cu and a solder cap, i.e., Cu pillar bumps. Figure 20 shows the evolution map of Cu pillar bumps.…”