PADRE: Physically-Aware Diagnostic Resolution Enhancement

Poku, Osei; Li, Xin; Blanton, R. D.

doi:10.1109/test.2013.6651899

Cited by 35 publications

(21 citation statements)

References 23 publications

(53 reference statements)

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“…They are usually concerned with two objectives: (a) defect identification, that is, mapping the diagnosed fault to a defect. This is challenging especially when it is based only on the failure response of the circuit (Gomez, Cook, Indlekofer, Hellebrand, & Wunderlich, 2017; L. R. Gómez & Wunderlich, 2016; Nelson et al, 2010); (b) improving diagnostic resolution, where the candidate faults are analyzed so as to further prune the set in order to improve the diagnostic resolution (Xue et al, 2013). The features used in both approaches are derived from the layout and logical information of the circuit and the output response of the failing chip.…”

Section: Yield Learning and Diagnosismentioning

confidence: 99%

“…As discussed in Section 2.4, the second approach towards fault diagnosis aims at processing the candidate faults to improve the diagnostic resolution. Most of the diagnostic tools produce a larger number of candidate faults compared to the actual number of faults (Xue et al, 2013). The efficiency of the ensuing steps of defect identification and PFA is thus impeded.…”

Section: Yield Learning and Diagnosismentioning

confidence: 99%

“…In order to improve the diagnostic resolution, we need to pare down the set of candidate faults. A classification‐based method similar to that in Nelson et al (2010) is proposed by Xue et al (2013) to label each candidate fault as either good or bad. A set of features is identified and thereafter the classification is performed in two steps: (a) the first one is rule‐based, which identifies some bad candidates; (b) the rest of the faults are analyzed by an SVM‐based classifier.…”

Section: Yield Learning and Diagnosismentioning

confidence: 99%

“…For the purpose of training, the labeled data available from PFA was not found to be so useful because of the fact that they are sparse and furthermore, being some kind of “old data,” they may introduce error when applied to new circuits. In order to alleviate these problems, Xue et al (2013) proposed a method to generate labeled data for each circuit: the defective chips, for which fault diagnosis yields a single candidate fault, are used to mark “good” candidate class. The chips for which the fault diagnosis provides a large number of candidate faults (greater than a threshold value) are used to mark “bad” candidate class.…”

Section: Yield Learning and Diagnosismentioning

confidence: 99%

“…In the area of digital logic testing, there are many opportunities for applying supervised learning. Various data sources that have been used or can be potentially used for ML applications in the field of digital electronic testing are listed below: Manufacturing test response: The failure response patterns of a volume of defective chips obtained during production testing can be used for diagnosis (Huisman, Kassab, & Pastel, 2004; Xue, Poku, Li, & Blanton, 2013). Simulation: A variety of labeled test data can be generated using simulation with CAD tools for testing.…”

Section: Introductionmentioning

confidence: 99%

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A survey of digital circuit testing in the light of machine learning

Pradhan

Bhattacharya

2020

WIREs Data Min & Knowl

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The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis. This article is categorized under: Algorithmic Development > Structure Discovery Technologies > Machine Learning Technologies > Prediction

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Section: Yield Learning and Diagnosismentioning

confidence: 99%

Section: Yield Learning and Diagnosismentioning

confidence: 99%

Section: Yield Learning and Diagnosismentioning

confidence: 99%

Section: Yield Learning and Diagnosismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A survey of digital circuit testing in the light of machine learning

Pradhan

Bhattacharya

2020

WIREs Data Min & Knowl

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Defect Diagnosis Techniques for Silicon Customer Returns

Girard¹,

Bosio²,

Ladhar³

et al. 2023

Frontiers of Quality Electronic Design (QED)

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This chapter provides an overview of the various approaches and techniques proposed so far for defect diagnosis in silicon customer returns. It focuses on diagnosis of defects in logic blocks of SoCs. After some backgrounds on test and fault diagnosis, the chapter presents the various test scenarios used in practice during customer return diagnosis. A discussion on the quality required by the test sequences used during customer return is also proposed. Then, the chapter reviews the stateof-the-art techniques existing to identify defects at the cell level (called intra-cell or cell-aware diagnosis). A summary of conventional approaches is first proposed. Then, the latest Machine Learning (ML) -based cell-aware diagnosis techniques are reviewed. Effectiveness of existing ML techniques is shown through industrial case studies and corresponding diagnosis results in terms of accuracy and resolution. The chapter ends with a discussion on the future directions in this field.

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Conventional Methods for Fault Diagnosis

Raman

2023

Machine Learning Support for Fault Diagnosis of System-on-Chip

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PADRE: Physically-Aware Diagnostic Resolution Enhancement

Abstract: Abstract

Cited by 35 publications

References 23 publications

A survey of digital circuit testing in the light of machine learning

A survey of digital circuit testing in the light of machine learning

Defect Diagnosis Techniques for Silicon Customer Returns

Conventional Methods for Fault Diagnosis

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