[Paper] A 3D Stacked 16Mpixel Global-shutter CMOS Image Sensor Using 4 Million Interconnections

Abstract

This means there are four million micro bumps in the pixel array area for 16 million effective pixels. The signals from readout circuit on the bottom substrate are transferred to the top substrate with micro bumps which are arrayed outside a pixel array area and readout to the outside of the chip through bonding pads in the bottom Abstract We have developed a 3D stacked 16Mpixel global-shutter CMOS image sensor with pixel level interconnections using four million micro bumps. The four photodiodes in the unit pixel circuit on the top substrate share one micro-bump interconnection in a 7.6µm pitch. Each signal of the photodiodes is transferred to the corresponding storage node on the bottom substrate via the interconnection to achieve a global-shutter function. The ratio of the parasitic light sensitivity of an in-pixel storage node and the light sensitivity of a photodiode is -180dB with a 3.8µm pixel. In addition, we discuss further improvement to reduce noise figure in global-shutter image sensors.

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

“…Even with the 100 dB difference in the illumination levels, all the color objects are clearly captured without saturation. A. Tournier et.al [3] T. Yokoyama et.al [5] M. Kobayashi et.al [6] L. Stark et.al [9] T. Kondo et.al [8] I. Takayanagi et.al [13,14] Process…”

“…A pixel-level interconnection [10] is needed to realize the GS operation and it is widely used in infrared focal-plane arrays, where an IR detector/pixel (not necessarily a Si detector) array is stacked with signal readout electronics built in Si integrated circuits together using a pixel-level micro-bump. The same approach was reported in pure Si devices [8]. With this approach, an extremely low PLS will be obtained, as the S/H capacitor that stores the signal voltage is fully shielded from any stray light.…”

“…Due to this structure, in the GS pixel, an additional in-pixel analog memory is needed to store the signal until it is read out from the pixel array. Generally, there are two approaches for the in-pixel analog memory; one is to store the signal charge before the charge-to-voltage conversion takes place, which is referred to as the charge domain GS pixel [1][2][3][4][5][6], and the other is to is to store a voltage signal after the charge is converted to a voltage, which is referred to as the voltage domain GS pixel [7][8][9]. These two approaches can be realized by both the front-side-illuminated (FSI) devices and the back-side-illuminated (BSI) devices.…”

“…These two approaches can be realized by both the front-side-illuminated (FSI) devices and the back-side-illuminated (BSI) devices. One more option that is considered for the voltage domain GS pixel is a stacked BSI approach [8]. In general, the charge domain GS pixel features relatively good noise performance, since correlated double sampling (CDS) can be employed to reduce noise.…”

“…A prototype CIS with 4.0 μm voltage domain GS pixels using a 45 nm/65 nm stacked CMOS process has been developed as a proof-of-concept vehicle. An additional capacitance is added in the first layer to realize single exposure high dynamic range (SEHDR) with dual conversion gains and/or is to store a voltage signal after the charge is converted to a voltage, which is referred to as the voltage domain GS pixel [7][8][9]. These two approaches can be realized by both the front-side-illuminated (FSI) devices and the back-side-illuminated (BSI) devices.…”