Parallel addition in digital computers: a new fast ‘carry’ circuit

Kilburn, T.; Edwards, D. Brent; Aspinall, David

doi:10.1049/pi-b-2.1959.0316

Cited by 18 publications

(4 citation statements)

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“…The carries generated and propagated depends only on the digits of the original numbers. Carry-skip scheme was proposed by Kilburn et al [2] it describes the technique to accelerate the carry propagation. A carry-skip adder reduces the time needed to propagate the carry by skipping over groups of consecutive adder stages.…”

Section: Introductionmentioning

confidence: 99%

Optimized area-delay and power efficient carry select adder

Kp¹,

Meenakumari²,

Sharmila³

2014

International Advanced Research Journal in Science, Engineering

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Abstract:In the design of Digital Integrated Circuits area occupancy, delay and power play an important role because of the increasing necessity of portable and fast systems. Adders are one of the most widely used digital components in various Digital Circuits. Carry Select Adder (CSLA) is one of the fastest adders used in many processors, multipliers, and different applications. Carry select method is having a good compromise between cost and performance in carry propagation method. In this paper a modified area and low power carry select adder along with lower delay is proposed. The proposed system has low area and power consumption with lower delay suitable for FPGA design than the existing carry select adders. Due to the optimized area, power and delay, the proposed CSLA design is a good substitution for all the existing CSLA. The proposed architecture is designed using VHDL and is then synthesized using XILINX 13.2i and is simulated in ISim for Spartan 3E FPGA.

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Section: Introductionmentioning

confidence: 99%

Optimized area-delay and power efficient carry select adder

Kp¹,

Meenakumari²,

Sharmila³

2014

International Advanced Research Journal in Science, Engineering

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“…In this paper we considered Carry-Skip (CSA) scheme [1], [2], [3], [4] because it met our objective of reasonable perf ormance achieved with a relatively small and regular area. This adder is in essence a Carry Lookahead for which the carrygenerate portion which consumes a large amount of logic, has been eliminated.…”

Section: Introductionmentioning

confidence: 99%

“…For a 48 bit adder we have, from Figure 2. xl = x7 = 4,~= x6 = 7, x3 = 8 and x4 = Xs = 9.Procedure 2:Fig.3. Carry chain of a 48-bit adder: T+(l-(-l) )8'(1) …”

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confidence: 99%

Some optimal schemes for ALU implementation in VLSI technology

Oklobdzija

Barnes

1985

1985 IEEE 7th Symposium on Computer Arithmetic (ARITH)

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An efficient scheme for carry propagation in an ALU implemented in n-MOS technology is presented. An algorithm that determines the optimwn division of the carry chain of a parallel adder for various data path sizes is developed. This yields an implementation of a fast ALU which due to its regular structure occupies a modest amount of silicon. The speed of the implementation described is comparable to the carry look-ahead scheme. Our method is based on the optimization of the carry path implemented in n-MOS technology but the results can be applied to other technologies.

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“…The first one is to use carry-skip adders [34] for higher speeds. With a regular snake-like layout all the wires, including the ones for skipping, could have the same minimum length, but incorporating redundancy will be a more difficult task.…”

Section: Discussionmentioning

confidence: 99%

On the Advantages of Serial Architectures for Low-Power Reliable Computations

Beiu

Aunet

Nyathi

et al.

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

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This paper explores low-power reliable microarchitectures for addition. Power, speed, and reliability (both defect-and fault-tolerance) are important metrics of system design, spanning device, gate, block, and architectural levels. The analysis considers the low power needs of future systems at supply voltages comparable to threshold voltages (V th ). Theoretical analysis and simulations show a decline of the speed advantages of parallel adders when considering wire delays. These evaluations suggest that serial adders might do better for (ultra) low-power operation, with redundancy for enhancing reliability. We analyze 32-bit multiplexed serial adders. The robustness when using output-wired mirrored adder (majority) gates is shown under faulty conditions. Simulations (at 180 nm, 120 nm, and 70 nm) identify the supply voltages where the power-delay-and energy-delay-products are minimized. These show that redundant serial adders are not only low-power and reliable, but can trade speed for power in a wide range (by varying V DD both above and below V th ).

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Parallel addition in digital computers: a new fast ‘carry’ circuit

Cited by 18 publications

References 0 publications

Optimized area-delay and power efficient carry select adder

Optimized area-delay and power efficient carry select adder

Some optimal schemes for ALU implementation in VLSI technology

On the Advantages of Serial Architectures for Low-Power Reliable Computations

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