Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

Paulin, Pierre; Pilkington, Chuck; Langevin, M.; Bensoudane, E.; Lyonnard, D.; Benny, Olivier; Lavigueur, Bruno; Lo, David; Beltrame, Giovanni; Gagné, Vincent; Nicolescu, Gabriela

doi:10.1109/tvlsi.2006.878259

Cited by 70 publications

(48 citation statements)

References 29 publications

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“…Certain other types of communication, such as the transfer of coarse grain data, can sometimes be achieved more efficiently through message passing, though it significantly increases the data management burden on the application programmer. The complementary nature of the sharedmemory and message-passing communication styles has recently led to the popularity of hybrid architectures, which implement the message-passing on top of distributed shared-memory architectures [1], [2], [3]. And a prominent example of such architecture is the Cell processor [4], jointly developed by IBM, Sony and Toshiba.…”

Section: Introductionmentioning

confidence: 99%

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Xiao

Isshiki

et al. 2012

IPSJ Transactions on System LSI Design Methodology

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Inter-processor communication and synchronization are critical problems in embedded multiprocessors. In order to achieve high-speed communication and low-latency synchronization, most recent designs employ dedicated hardware engines to support these communication protocols individually, which is complex, inflexible, and error prone. Thus, this paper motivates the optimization of inter-processor communication and synchronization by using application-specific instruction-set processor (ASIP) techniques. The proposed communication mechanism is based on a set of custom instructions coupled with a low-latency on-chip network, which provides efficient support for both data transfer and process synchronization. By using state-of-the-art ASIP design methodology, we embed the communication functionalities into a base processor, making the proposed mechanism feature ultra low overhead. More importantly, industry-standard compatible programming interfaces supporting both message-passing and shared-memory paradigms are exposed to end-users to ease the software porting. Experimental results show that the bandwidth of the proposed message-passing protocol can achieve up to 703 Mbyte/s @ 200 MHz, and the latency of the proposed synchronization protocol can be reduced by more than 81% when compared with the conventional approach. Moreover, as a case study, we also show the effectiveness of the proposed communication mechanism in a real-life embedded application, WiMedia UWB MAC.

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Section: Introductionmentioning

confidence: 99%

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Xiao

Isshiki

et al. 2012

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

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“…In [3], the MultiFlex uses the object request broker (ORB) to connect client task to the server task. The aim is to accelerate the scheduling and synchronization message passing among tasks.…”

Section: Related Workmentioning

confidence: 99%

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System

Yang

Wu³

et al. 2011

Lecture Notes in Computer Science

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Abstract. How to manage the message passing among inter processor cores with lower overhead is a great challenge when the multi-core system is the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. Generally speaking, the networks-on-chip connects the distributed multi-core system. It takes charge of message passing which including data and synchronization message among cores. The size of most data transmission is typically large enough that it remains strongly bandwidth-bound. The synchronization message is very small which is primarily latency bound. Thus the separated networks-on-chip are needed to transmit the above two types of message. In this paper we focus on the network for the transmission of synchronization messages. A hardware module -message passing unit (MPU) is proposed to manage the synchronization message passing for the heterogeneous multi-core system. Compared with the original single network approach, this solution reduces the run-time object scheduling and synchronization overhead effectively, thereby, improving the whole system performance.

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“…The function has to be executed 2 * N − 2 times as specified by the polytope in lines 12-13. The value of N is between 3 and 384 (lines [14][15]. From the XML specification, Daedalus allows for automatically generating the C/C++ code implementing the behavior of each KPN process.…”

Section: Parallelizing Applicationsmentioning

confidence: 99%

“…Work focusing on the mapping of applications onto MP-SoCs, in the form of programming models, can be found in, e.g., [14,6].…”

Section: Related Workmentioning

confidence: 99%

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

Thompson

Nikolov

Stefanov

et al. 2007

Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology with the (parallelized) application mapped onto it in only a matter of hours. During this traversal, which offers a high degree of automation, guidance is provided by Daedalus' integrated system-level design space exploration environment. We show that Daedalus offers remarkable potentials for quickly experimenting with different MP-SoC architectures and exploring system-level design options during the very early stages of design. Using a case study with a Motion-JPEG encoder application, we illustrate Daedalus' design steps and demonstrate its efficiency.

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Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

Cited by 70 publications

References 29 publications

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

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