Parameterized models for a RF chip-to-substrate interconnect

Abstract

Skyrocketing growth in the cellular personal communications services (PCS) sector has fueled the needs for higher density, more functionality, and greater performance on both handset and basestations. Third generation wireless standards, which require hardware upgrades, loom on the horizon. RF component suppliers are scrambling to find solutions at the IC, package, and PCB levels to meet these challenges. RF module packaging is considered as one of the low cost solutions to the future wireless products. One of the critical design needs for RF interconnects is to understand the electrical performance of wire bond (the RF interconnect of choice) at and above frequency of interest, and to determine the performance limit for the wire bond chip-to-substrate interconnect. The availability of design kit or library would result in a substantial reduction in design cycle times. Using wire bond as example, this paper illustrates the developmental stages that turn electromagnetic characteristics of a physical structure into design library. Fullwave simulation using Ansoft HFSS and compact models extraction using optimization tool for wire bond will be shown, followed by in-depth discussions of wire bond parameterized models. Validation of parameterized model by measurement will be presented. IntroductionRF module packaging has many advantages: favorable pricing power being the most important one, as opposed to cost-based pricing at the sum of the individual ICs and embedded passives costs. The module packaging can also benefit the system integrators who are less skillful in RF design and skills. This ease of use leads to proliferation of RF module demands. Design tools or libraries for module are one of the critical paths that enable a full adoption of the module technology.In this paper, the parameterized electrical compact (RLC) models of wire bonds (the RF interconnect of choice) are shown. Since interconnects are relatively independent of the substrate of choice, development of interconnect models need not be repeated as substrate of choice changes. Since LTCC allows an easy implementation of different die height (or thickness) using cavity, it is used in wire bond interconnect models development. Using mainly single wire bonds as example, the design tool development methodology is illustrated. First, the design space and Design of Experiment (DOE) for wire bonds are described, followed by Ansoft

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