Parameterized path-based, randomized, oblivious, minimal routing in 3D mesh NoC

Ahmed, Mushtaq; Kumar, Rakesh

doi:10.1109/tencon.2012.6412341

Cited by 4 publications

(1 citation statement)

References 15 publications

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“…At each level, there is the computation of intermediate nodes whose buffer capacity is measured and based on the availability of buffer and congestion status, the packets (flits) move forward so they can handle the optimal path in congested routes. PROM3D is efficient for latency and throughput [34] as it always finds minimal paths at each hop by choosing the higher probability of less congestion paths and larger buffer on the cost of increased power consumption due to computational overhead and use of VCs. As it needs a minimum of two VCs so the number of buffer reads/writes operations shall be higher.…”

Section: Performance Analysismentioning

confidence: 99%

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Ahmed,

Ambudka,

Yadav

2024

ISI

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The Network-on-Chip (NoC) stands as a potent solution for achieving heightened performance, efficient communication, and dependability in the migration of Very-Large Scale Integration (VLSI) architecture toward deep submicron technology, when contrasted with conventional connectivity networks. Considerable research endeavours have been allocated to diverse facets of NoCs, encompassing topology, routing algorithms, traffic behaviours, power management, and fundamental mapping. This paper explores the power consumption efficiency of Parameterized Path-Based, Randomized, Oblivious, Minimal for 3D Mesh (PROM3D) routing and ZXY routing algorithms for various traffic patterns like transpose, bit shuffle, and random traffic with the help of the integrated DSENT network model. The PROM3D routing algorithm selects a path randomly from all possible minimal pathways between the source and destination, whereas ZXY is a layer-based routing method. The Design Space Exploration of Network (DSENT) tool is used with the NoC Interconnect Routing and Applications Modeling (NIRGAM) simulator in experiments to measure the power consumption. The findings indicate that, within the 3D-Mesh environment, the ZXY routing algorithm exhibits a 0.02% of variation in power consumption while in saturation on varying loads for various traffic patterns in comparison to the PROM3D algorithm.

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Section: Performance Analysismentioning

confidence: 99%

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Ahmed,

Ambudka,

Yadav

2024

ISI

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3D NoC: a promising alternative for tomorrow's nanosystem design

Ghosal¹,

Das²,

Poddar³

et al. 2016

Nano-Cmos and Post-Cmos Electronics: Circuits and Design

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The impact of routing arbitration mechanisms on 3D NoC latency

Cataldo

Fernandes

Grando

et al. 2014

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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This paper discusses the impact of routing arbitration mechanism on the packet latency for 3D NoC (Three-dimensional Network-on-Chip) architectures. We implemented several variations of Round-Robin mechanisms to explore how the arbitration efficiency affects the packet latency. The underlying objective is to discuss the compromise of increase router area and energy consumption through investing on a complex low-clock cycle router compared with a simpler but energy and area efficient router. The experimental setup is composed of two sizes of 3D mesh NoC, synthetic traffic pattern and several injection rates. Results demonstrate that the increase of arbitration latency does not affect proportionally the packet latency. In fact, for low traffic injection rates the arbitration algorithm does not influence the average of packet latency significantly, justifying the approach of employing less complex routers with less impact on area and energy consumption.

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Parameterized path-based, randomized, oblivious, minimal routing in 3D mesh NoC

Cited by 4 publications

References 15 publications

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network

3D NoC: a promising alternative for tomorrow's nanosystem design

The impact of routing arbitration mechanisms on 3D NoC latency

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