3D NoC-based architectures have emerged to reduce the network latency, the energy consumption and total area in comparison to 2D NoC topologies. However, they are characterized by various trade-offs with regard to the three dimensional structure and its performance specifications. In this paper, we present a 3D NoC mesh architecture called Lasio, whose latency and the throughput achieved, for both network and application, are evaluated considering two types of traffic patterns, varied buffer depth and a range of packet sizes. Cycle-accurate simulations demonstrated that there is a high impact of buffer depth and packet size on the NoC latency and on the application latency. Applying an appropriate buffer depth, for several sizes of packets, the application latency is reduced and throughput is increased.

This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses of Tiny NoC. The experimental results highlight that Tiny NoC always reduces area occupancy and for several cases it provides latency minimization.

Tiny is a scalable and efficient three-dimensional (3D) network-onchip (NoC) designed to reduce latency and area. A theoretical analysis demonstrates its efficiency when compared with a basic 3D mesh NoC. Mapping independent traffics with different injection rates makes the trade-offs analysis of Tiny possible. Results highlight that Tiny always reduces area and for several cases minimises latency.

This paper discusses the impact of routing arbitration mechanism on the packet latency for 3D NoC (Three-dimensional Network-on-Chip) architectures. We implemented several variations of Round-Robin mechanisms to explore how the arbitration efficiency affects the packet latency. The underlying objective is to discuss the compromise of increase router area and energy consumption through investing on a complex low-clock cycle router compared with a simpler but energy and area efficient router. The experimental setup is composed of two sizes of 3D mesh NoC, synthetic traffic pattern and several injection rates. Results demonstrate that the increase of arbitration latency does not affect proportionally the packet latency. In fact, for low traffic injection rates the arbitration algorithm does not influence the average of packet latency significantly, justifying the approach of employing less complex routers with less impact on area and energy consumption.