Partial scan design methods based on internally balanced structure

Abstract

In this paper, we theoretically and experimentally show the eectiveness of partial scan design based on internally balanced structure, which is a sequential circuit capable of generating tests with a combinational test generation algorithm. Moreover, we i n troduce a method of extended partial scan design, which replaces part of not only ip-ops by scan ip-ops but also wires by bypass ip-ops in a sequential circuit, and propose a method of extended partial scan design based on internally balanced structure. Experimental results for benchmark circuits show that the proposed partial scan design and extended partial scan design can be implemented with low area overhead.

Test sequence compaction methods for acyclic sequential circuits using a time expansion model

“…(2) the length of a test sequence needed in order to attain high fault efficiency, or the testing time of the LSI tester. tial circuit, high fault efficiency can be obtained with smaller hardware overheads than in full scan design [6][7][8][9]. In particular, in Ref.…”

“…In partial scan design, selection of the flip-flop (FF) of the circuit that is to be replaced by the scan FF is a major problem. It is known that test generation is possible for acyclic sequential circuits by a combinational test generation algorithm [6][7][8][9]. Hence, by selecting the scan FF in a way that makes the core circuit (the circuit after removing the scan FF) an acyclic sequen-…”