Passivation of Ge surface treated with trimethylaluminum and investigation of electrical properties of HfTiO/Ge gate stacks

Atomic layer deposited tantalum silicate on crystallographically-oriented epitaxial germanium: interface chemistry and band alignment

“…70 A moderate range of bandgap values, between 4.4 eV–4.65 eV, have been reported in the literature, with variability in the measured bandgap stemming from the deposition method(s) utilized, or empirical method in determining the oxide bandgap (including XPS, photoluminescence and photoemission spectroscopies) of Ta 2 O 5 . 34–44 Cevro et al 39 reported an optical bandgap varying from 4.3 eV–9.0 eV for x = 1.0 to x = 0.0 atomic mole fraction of Ta 2 O 5 in the composite (Ta 2 O 5 ) 1− x (SiO 2 ) x dielectric. However, Adelmann et al 40 found that for ALD TaSiO x on Si, the bandgap starts to vary from ∼4.5 eV for x = 0.0 up to ∼4.9 eV for x = 0.5.…”

“…In order to address the above challenges, extensive dielectric research has been performed over the last two decades, with little success in finding simple (non-composite, or non-binary) dielectric systems that mimic the electrical and thermodynamic stability of the SiO 2 /Si interface. 4–38 One promising dielectric, tantalum oxide (Ta 2 O 5 ), and its silicate (TaSiO x or (Ta 2 O 5 ) 1− x (SiO 2 ) x ), has recently found renewed interest as a potential high- κ dielectric for the Ge 39–49 and III–V 50–53 material systems. TaSiO x was shown to achieve excellent device performance when integrated within a composite TaSiO x /InP gate stack (on In x Ga 1− x As-channel FETs), exhibiting low interfacial defect density ( D it ), low gate leakage current density ( J g ), and high drive current ( I ON ).…”

Oxidation Mechanisms of Hafnium Overlayers Deposited on an Si(111) Substrate

“…Hafnium dioxide (HfO 2 ) is a desirable (high-κ) material in Si-based metal-oxide–semiconductor field-effect transistors (MOSFETs) because of its high dielectric constant (κ ≈ 21), large band gap (≈5.7 eV), high thermal stability on a Si substrate, and low density of electrically active defects at the oxide/silicon interface. , In recent years, advanced research on HfO 2 -based high-κ dielectrics and their fundamental properties on semiconductor substrates, except for silicon, has been reported. − However, several studies have thermodynamically examined the early oxidation mechanism of a few hafnium monolayers (MLs) deposited on Si substrates. Furthermore, there are no clear observations of the resulting local bonding configurations at the interface or details of the oxidation states on their surfaces.…”

Impact of ZrO2 Dielectrics Thickness on Electrical Performance of TiO2 Thin Film Transistors with Sub-2 V Operation

“…Most of our attention in our previous work has been focused on the TiO 2 channel and its material properties upon O 2 annealing; the effects of gate dielectrics on the electrical performance of TFTs have not been investigated. Theoretically speaking, a reduced dielectric thickness could unequivocally enhance device performance, originating from an improved electrostatic control of the gate. − However, in practice, dielectric thickness scaling in the nanometer regime can be a challenge, which poses stringent demands on the dielectric quality. , The challenges for dielectric thickness scaling could be summarized as follows: (1) The leakage current exponentially increases as the dielectric thickness reduces, thereby impairing the overall device performance. ,, (2) The oxide charges in the gate dielectric may be varied by thickness, causing instability of the threshold voltage ( V th ) and degradation of the channel mobility (μ eff ) in devices. , (3) The interface chemistry and the interface trap of the dielectric/channel junction might also be dependent on the dielectric thickness for aggressive thickness scaling, leading to the modification of the electrical characteristics of TFTs. , Although there have been reports showing high-performance TFTs with ultrathin dielectrics, − most of these reports have focused on analyzing the TFT performance with the thinnest possible dielectric, solving challenge (1) for scaled dielectrics but leaving challenge (2) and (3) not addressed. A comprehensive study of the impact of dielectric thickness on TFT performance would reveal the behaviors of leakage current, oxide capacitance, oxide charges, and interface traps with respect to the dielectric thickness and shed light on the quality and scalability of gate dielectrics, which can be extended to other material systems.…”

“…34−38 However, in practice, dielectric thickness scaling in the nanometer regime can be a challenge, which poses stringent demands on the dielectric quality. 39,40 The challenges for dielectric thickness scaling could be summarized as follows: (1) The leakage current exponentially increases as the dielectric thickness reduces, thereby impairing the overall device performance. 36,41,42 (2) The oxide charges in the gate dielectric may be varied by thickness, causing instability of the threshold voltage (V th ) and degradation of the channel mobility (μ eff ) in devices.…”