PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor

Li, Minghua; Chen, Guancheng; Wang, Qijun; Lin, Yu; Hofstee, Peter; Stenström, Per; Zhou, Dian

doi:10.1109/lca.2015.2442972

Cited by 11 publications

(20 citation statements)

References 3 publications

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“…Few research has been done when referring to parallel workloads. Li et al [45] apply a machine learning model to predict the best settings for the data prefetcher in different parallel workloads. Their search space is small compared to our work and they do not consider possible interactions between knobs.…”

Section: Data Prefetchingmentioning

confidence: 99%

Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption

Ortega

Alvarez

Casas

et al. 2021

IEEE Trans. Comput.

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Current microprocessors include several knobs to modify the hardware behavior in order to improve performance, power, and energy under different workload demands. An impractical and time consuming offline profiling is needed to evaluate the design space to find the optimal knob configuration. Different knobs are typically configured in a decoupled manner to avoid the time-consuming offline profiling process. This can often lead to underperforming configurations and conflicting decisions that jeopardize system power-performance efficiency. Thus, a dynamic management of the different hardware knobs is necessary to find the knob configuration that maximizes system power-performance efficiency without the burden of offline profiling. In this paper, we propose libPRISM, an infrastructure that enables the transparent management of multiple hardware knobs in order to adapt the system to the evolving demands of hardware resources in different workloads. libPRISM can minimize execution time, energy-delay product or power consumption by dynamically managing the SMT level, the data prefetcher, and the DVFS hardware knobs. Overall, the proposed solutions increase performance up to 130% (16.9% on average), reduce energy-delay product up to 80%, and reduce power consumption up to 33% depending on the target metric compared to the default knob configuration of the system.

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Section: Data Prefetchingmentioning

confidence: 99%

Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption

Ortega

Alvarez

Casas

et al. 2021

IEEE Trans. Comput.

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“…The work in [21] reports an 8% increase on average in performance from applying AREP. The automatic prefetching tuner (PATer) for the POWER8 processor [22] provides a way of tuning the prefetch configuration.…”

Section: Investigation Of These Intermediate Hardware Buffers or Cachmentioning

confidence: 99%

“…However, to apply PATer requires an offline training phase with representative workloads. The authors of [22] report a 1.4 improvement in processing speed but do not consider energy consumption. Again, tuning is for a cache-based system, not the cache-less processors considered in this paper.…”

Section: Investigation Of These Intermediate Hardware Buffers or Cachmentioning

confidence: 99%

Energy-efficient data prefetch buffering for low-end embedded processors

Qadri

Fleury

et al. 2017

Microelectronics Journal

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An energy-efficient architecture should jointly optimize energy consumption and throughput, as captured by the Energy-Delay-Square Product (ED 2 P) metric. This paper introduces a prefetch data buffer microarchitecture, which achieves that goal with the aid of software-inserted control words to govern the prefetch process. The proposed architecture is aimed at low-end embedded processors, which, so as to reduce energy consumption, lack a cache-based memory hierarchy. By identifying after compilation which data should be prefetched and modifying the object code, the rate of prefetch misses is reduced. And by pre-computing memory addresses using auxiliary software after compilation and modifying the object code, address computation by hardware at run time is avoided, reducing pipeline stalls and, thus, improving throughput. Additionally in the case of branches, by prefetching two data items at any one time, alternative instruction outcomes are anticipated. The paper contains results from running a range of well-known and representative benchmarks on the proposed architecture. There was an improvement of 6%−20% compared to an unbuffered architecture in execution times when tested over those seven benchmarks. Furthermore, the average ED 2 P for the buffered architecture when normalized against the same architecture without buffering was found to vary between 54% − 90% according to benchmarking, though there is a cost in code size increase. That is to say, for the benchmarks tested there was a net energy efficiency improvement of between 10% and 46% in comparison with the equivalent unbuffered architecture with a lower area overhead.

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“…The mechanism provides the opportunity to turn off the prefetcher but only in those cases where prefetching hurts the system performance, and no policy is devised to turn on the prefetcher again. More recently, PATer [52] has been proposed. It uses a prediction model based on machine learning with the aim of dynamically tuning the prefetcher parameters of the IBM POWER8, which has 2 25 possible configurations.…”

Section: Prefetchingmentioning

confidence: 99%

“…applications) compete with regular memory requests for off-chip main memory bandwidth. Therefore, since prefetching is a speculative technique, it increases the total number of accesses to main memory [6,52,25]. In scenarios of high memory bandwidth consumption, this fact can turn into significant performance losses in some individual applications, which are affected by the prefetches of their co-runners.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Prefetching and Cache Partitioning for Multicore Processors

Oliver¹

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Accessing main memory represents a major performance bottleneck in current processors, since the different cores compete among them for the limited offchip bandwidth, aggravating even more the so called memory wall. Several techniques have been applied to deal with the core-memory performance gap, with the most preeminent ones being prefetching and hierarchical caching. Hierarchical caches leverage the temporal and spacial locality of the accessed data, mitigating the huge main memory access latencies. To limit the number of accesses to the off-chip DRAM memory, current processors feature large Last Level Caches. These caches are shared between all the cores to improve the utilization of the cache space and reduce cost. This approach significantly improves the performance of most applications compared to using smaller private caches. Cache sharing, however, presents an important shortcoming: the interference between applications. Prefetching, on the other hand, brings data blocks to the caches before they are requested, hiding the main memory latency. Unfortunately, since prefetching is a speculative technique, inaccurate prefetches may pollute the cache with blocks that will not be used. In addition, the prefetches interfere with the regular memory requests, both the ones from the application running on the core that issued the prefetches and the others.

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PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor

Cited by 11 publications

References 3 publications

Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption

Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption

Energy-efficient data prefetch buffering for low-end embedded processors

Adaptive Prefetching and Cache Partitioning for Multicore Processors

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