“…When using this approach, it is possible to cut path lengths of the combinational circuits and cut the number of OR, AND, NOT gates if we implement XOR as a sub-circuit from these gates. It is revealed that PDFs in the resulted circuits (similar circuits are considered in [7]) manifest themselves either as robust testable or as validatable non robust testable ones. When applying test pairs in the definite order, we may detect any PDF of the circuit.…”