Performance Analysis and Enhancement of Negative Capacitance Logic Devices Based on Internally Resistive Ferroelectrics

Hsu, Chia-Sheng; Pan, Chenyun; Naeemi, Azad

doi:10.1109/led.2018.2820118

Cited by 13 publications

(7 citation statements)

References 14 publications

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“…Based on Landau-Ginzburg-Devonshire phenomenological theory, if ferroelectric material undergoes a second order phase transition, then α<0, β>0 and γ=0 in Landau equation. Moreover, the value of ρ was estimated as mentioned in [14]- [16].…”

Section: Spice Model and Simulation Methodsmentioning

confidence: 99%

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Huang

Zhu

et al. 2020

IEEE J. Electron Devices Soc.

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In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) NWFET) were analyzed by employing the custom-built SPICE model. In the simulation, the minimum subthreshold swing (SS) reduced to 40 mV/decade with negligible hysteresis, and the on-current amplified by approximately three times. The N-DIBL effect was analyzed by building a model, and the results indicated that the N-DIBL is negatively correlated with the SS. Hence, it is indispensable to make trade-offs between the N-DIBL and SS in NC NWFET applications. Moreover, the Miller effect of a NCFET-based inverter was investigated for the first time. The Miller effect of the NC NWFET-based inverter was considerably improved owing to a high on-current and negative internal gate voltage (when external gate voltage is set to 0V), which is beneficial for high-speed circuit building based on NC NWFETs. The overshoot of the NC NWFET-based inverter is ~43.1% less than that of the NWFET-based inverter, and the propagation delay of the NC NWFET-based inverter is ~73.1% less than that of the NWFET-based inverter at ferroelectric thickness TFE=3nm.

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Section: Spice Model and Simulation Methodsmentioning

confidence: 99%

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Huang

Zhu

et al. 2020

IEEE J. Electron Devices Soc.

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“…Because the interactions of the highly non‐linear FE capacitor with gate capacitances present in the devices and circuits lead to unconventional characteristics, the overall theoretical analysis at the circuit level is highly complicated and warrants further investigation [9–12]. In particular, the impact of the NC effect on the timing characteristic in NCFET‐based CMOS circuits has not been evaluated adequately [11, 13, 14]. Improvement in the inverter delay performance can be achieved because of the large current gain in NC‐FinFETs provided by the FE layer, but the compact model used in [11] is weakly accurate as compared to TCAD simulation with the finite element method.…”

Section: Introductionmentioning

confidence: 99%

“…Improvement in the inverter delay performance can be achieved because of the large current gain in NC‐FinFETs provided by the FE layer, but the compact model used in [11] is weakly accurate as compared to TCAD simulation with the finite element method. Hsu et al [13] confirmed that under the low viscosity coefficient of FE capacitors, the propagation delay becomes smaller when the NCFET interconnect is operated at a high supply voltage as compared to the baseline CMOS logic circuit.…”

Section: Introductionmentioning

confidence: 99%

Performance improvement of timing and power variations due to random dopant fluctuation in negative‐capacitance CMOS inverters

Zhang

Lü

et al. 2020

IET Circuits, Devices & Systems

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“…The physical concept behind this approach is that the metastable negative capacitance (NC) state arising from the doublewell energy profile of the FE can be stabilized by the DE layer in terms of the total free energy of the system. Such a proposal may provide a potential way to significantly improve the subthreshold swing of conventional complementary metal-oxide-semiconductor (CMOS) transistors at room temperature [4,5].…”

Section: Introductionmentioning

confidence: 99%

Physical Mechanism behind the Hysteresis-free Negative Capacitance Effect in Metal-Ferroelectric-Insulator-Metal Capacitors with Dielectric Leakage and Interfacial Trapped Charges

Hsu,

Chang,

Nikonov

et al. 2020

Preprint

Self Cite

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The negative capacitance (NC) stabilization of a ferroelectric (FE) material can potentially provide an alternative way to further reduce the power consumption in ultra-scaled devices and thus has been of great interest in technology and science in the past decade. In this article, we present a physical picture for a better understanding of the hysteresis-free charge boost effect observed experimentally in metal-ferroelectric-insulator-metal (MFIM) capacitors. By introducing the dielectric (DE) leakage and interfacial trapped charges, our simulations of the hysteresis loops are in a strong agreement with the experimental measurements, suggesting the existence of an interfacial oxide layer at the FE-metal interface in metal-ferroelectric-metal (MFM) capacitors. Based on the pulse switching measurements, we find that the charge enhancement and hysteresis are dominated by the FE domain viscosity and DE leakage, respectively. Our simulation results show that the underlying mechanisms for the observed hysteresis-free charge enhancement in MFIM may be physically different from the alleged NC stabilization and capacitance matching. Moreover, the link between Merz's law and the phenomenological kinetic coefficient is discussed, and the possible cause of the residual charges observed after pulse switching is explained by the trapped charge dynamics at the FE-DE interface. The physical interpretation presented in this work can provide important insights into the NC effect in MFIM capacitors and future studies of low-power logic devices.

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Performance Analysis and Enhancement of Negative Capacitance Logic Devices Based on Internally Resistive Ferroelectrics

Cited by 13 publications

References 14 publications

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Performance improvement of timing and power variations due to random dopant fluctuation in negative‐capacitance CMOS inverters

Physical Mechanism behind the Hysteresis-free Negative Capacitance Effect in Metal-Ferroelectric-Insulator-Metal Capacitors with Dielectric Leakage and Interfacial Trapped Charges

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