Performance analysis of low power and high speed 16-Bit CRC Generator using GDI technique

Kandasamy, Nehru; Babu, M. Ramesh; Sravana, J.; Reddy, S. V. Raghu Sekhar

doi:10.1109/icaccs.2016.7586358

Cited by 3 publications

(1 citation statement)

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“…The result shows the Kogge stone adder outperformed the other conventional adders in terms of speed with increase in die area [21]. The power consumption and transistor count can be reduced by GDI technique [22]. [23] Designed and implemented Kogge stone adder using CMOS and GDI logic and simulated using Cadence design suite for 180nm technology.…”

Section: Related Workmentioning

confidence: 99%

Design and Analysis of Braun Multiplier Using CMOS/GDI Technique for Signal Processing

2020

IJETER

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Efficient arithmetic circuits are needed for cost effective and computation intense signal processing applications. Electronic appliances such as pagers, notebook computers and laptops demands high reliable and portable circuits. With the advent of high performance chips, power dissipation has gained its importance for efficient chip design. The need to explore efficient design techniques has increased to achieve high throughput and reduced power dissipation. Addition is an obligatory and crucial arithmetic operation used in application specific and general purpose systems. This paper discusses the design of efficient adder and its implementation in Braun multiplier using different logic styles like Gate Diffusion Input (GDI) logic and Complementary Metal Oxide Semiconductor (CMOS). The design is implemented in Cadence Virtuoso tool for 45 nm technological node. The GDI logic style reduces the delay of Braun multiplier by 42.38% with power optimization compared with CMOS logic style.

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Section: Related Workmentioning

confidence: 99%