Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices

Abstract

In this paper, the effects of large-tilted-angle p-pocket (LAP) implantation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 45° LAP cell featuring a fastest programming speed, however, would not be desirable due to the seriously aggravated read current degradation, drain/read disturbance, and early snap-back breakdown. The cells with 0° and 30° tilted angle are the feasible cells with the moderate programming performance and acceptable reliability constraints. Furthermore, the 0° LAP cell is preferred for the fact that it exhibits the desirable read current than that in 30° cell. Based on the cell performance and reliability consideration, the 0° p-pocket implanted cell is the optimal angle among 0°, 30° and 45° for the future scaling of stacked-gate memory cell.

Optimal Channel Doping Profile of Two-Dimensional Metal-Oxide-Semiconductor Field-Effect Transistors via Geometric Programming

“…Figure 3(a) shows the 1D section doping profile along the channel direction at the surface of the channel and the optimized doping profiles decay from source/drain end to the channel center. Notably, the shape of these "pocket" doping profiles could be obtained by a large tilted-angle implantation [7,43]. This type doping profile engineering delays the threshold voltage roll-off due to the SCE.…”

“…The Leff is discretized with M uniformly spaced points yj = jLeff/M, j = N, N+1,…, N+M-1, as shown Fig. 1(b), and the Wdm is discretized as (6)- (7). The doping profile is then defined as: dij = NA(xi, yj), i = 0, 1,…, K-1, j = N, N +1,…, N+M-1.…”

“…which is a function of doping profile dij in Region II. For obtaining the WD, the technique is similar to (3) to (7) except that we have to change the boundary condition and the index of the integral from Region I to Region III. We express the WD as a function of doping profile dij:…”

“…governs the device performance, affects the short-channel effect (SCE) [1][2][3][4][5][6][7], and regulates the random-dopant-fluctuation-induced threshold voltage fluctuation (RDF-induced Vt) [8][9][10][11][12][13]15] significantly. However, various doping-profile designs strongly rely on device engineering experiences in process/device simulation and fabrication experiment, such as retrograde doping profile method [6], methodology of inverse modeling using I-V characteristics [14], simulation-based evolutionary technique [15] and regression method [16].…”