No abstract

In this paper, the effects of large-tilted-angle p-pocket (LAP) implantation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 45° LAP cell featuring a fastest programming speed, however, would not be desirable due to the seriously aggravated read current degradation, drain/read disturbance, and early snap-back breakdown. The cells with 0° and 30° tilted angle are the feasible cells with the moderate programming performance and acceptable reliability constraints. Furthermore, the 0° LAP cell is preferred for the fact that it exhibits the desirable read current than that in 30° cell. Based on the cell performance and reliability consideration, the 0° p-pocket implanted cell is the optimal angle among 0°, 30° and 45° for the future scaling of stacked-gate memory cell.

The analysis of modulation-broadened experimental magnetic resonance spectra by the fitting of theoretical lineshape functions is described together with tests on zero field NMR lineshapes from 69Co in cubic cobalt. It is shown that for small modulation amplitudes values for the resonance width, intensity and mode admixture may be obtained. For large modulation amplitudes considerable errors may occur in the deduced values of intensity and width but their ratio, the resonance amplitude, is still accurately determinable. The application of correction curves to spectral parameters of resolved lines is summarized.

This paper describes and discusses intensively the charge loss characteristics in the stacked-gate memory device with interpoly oxide-nitride-oxide (ONO) dielectric at elevated temperatures. There exist two distinct phases in the charge loss characteristics. The dominant mechanism in the first phase can be described as the charge transport in the nitride layer. The second phase is dominated by effective thermionic emission effect from the stacked gate system. A linearly proportional relationship is also observed between normalized charge loss in the first phase and initial threshold voltage shift. Due to the fast charge loss rate, the charge loss in the first phase governs the threshold instability of the stacked-gate device. A method to determine the programming window for better threshold voltage stability based on charge loss in first phase is proposed.

We propose a novel operation scheme for multilevel p-channel flash memory cell with a self-convergent programming process. By utilizing the simultaneous Fowler-Nordheim electron tunneling out of floating gate and channel hot electron injection into floating gate, the threshold voltage of memory cell can be converged to a specific value. The gate pulse level can be varied to result in different converged threshold voltages such that multilevel can be achieved. Owing to the nature of self-convergence, the possibility of eliminating or reducing the verification operation in multilevel applications increases considerably by using the proposed scheme. In this study the reliability considerations of this programming technique for long-term operations are also addressed.