Performance Enhanced Unsymmetrical FinFET and its Applications

Patel, Govind Singh; Tripathi, Suman Lata; Awasthi, Sandhya

doi:10.1109/edkcon.2018.8770411

Cited by 9 publications

(1 citation statement)

References 12 publications

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“…The advanced MOSFET other than conventional NMOS and PMOS can be used to design SAR ADC architecture for future performance improvements. Mostly advanced MOSFETs like Vertical channel MOSFET, FinFET, nanowire or TFET [44][45][46] are explored for digital logic application. So, there is scope to use such efficient transistors for future analog circuit design and applications.…”

Section: Performance Specifications Of Presented Design Of Sar Adcmentioning

confidence: 99%

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Singh,

Tripathi,

Kumar

2024

JICS

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In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

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Section: Performance Specifications Of Presented Design Of Sar Adcmentioning

confidence: 99%