Performance Enhancement by Optimization of Poly Grain Size and Channel Thickness in a Vertical Channel 3-D NAND Flash Memory

Bhatt, Upendra Mohan; Kumar, Arvind; Manhas, S. K.

doi:10.1109/ted.2018.2817920

Cited by 20 publications

(7 citation statements)

References 15 publications

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“…It should be noted that the relatively high operation voltages of ±15 V and pulse widths of 20 ms are due to the use of a thick gate oxide stack with a total thickness of 140 nm. Nevertheless, this operation conditions are comparable with those of conventional flash memory using much thinner gate stack with about 20 nm in thickness [19]. Therefore, the pulse amplitude and width are expected to be further reduced by scaling down the gate stack thickness.…”

Section: Resultsmentioning

confidence: 56%

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Han

Jeong

Kim

et al. 2022

Materials Today Advances

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Section: Resultsmentioning

confidence: 56%

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Han

Jeong

Kim

et al. 2022

Materials Today Advances

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“…NAND technology currently uses a three-dimensional (3-D) structure and polysilicon as the channel material [4]. However, when implementing multi-level technology and high-rise stacking technology to enhance efficiency, several factors affect the variability of 3-D NAND flash memories, and these factors can be classified into three categories [5]: the effect of grain boundary traps [6][7][8][9], fluctuations in the control of the critical dimension [10], and the effect of the tapered channel [11][12][13]. Among these factors, the taper angle and the mold height are major reasons for the string performance differences between the top and the bottom cells as the number of cells is increased.…”

Section: Introductionmentioning

confidence: 99%

Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories

Lee

Jung

Park

et al. 2021

IEEE J. Electron Devices Soc.

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The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (∆VT) between the cells. The difference in ∆VT between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories. Index Terms-3-D NAND flash memories, threshold voltage shift, tapered channel

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“…However, little studies simultaneously consider grains' random distribution and contact deformations. Additionally, particles' wear also has a significant effect on undeformed chip thickness as different wear states could produce dissimilar material removal behaviors during grinding [14]- [16]. Numerous researches have investigated the grit wear behavior based on a single grain [17]- [20].…”

Section: Introductionmentioning

confidence: 99%

“…Results demonstrate that the rake angle, grain shape, and grinding load has great influence on the wear resistance of abrasive grains. However, only the qualitative analysis of the abrasive wear are conducted by the majority of researches [15], [16], [23]- [26], and it has not been converted into the impact on the undeformed chip thickness.…”

Section: Introductionmentioning

confidence: 99%

Modeling of the Distribution of Undeformed Chip Thickness Based on the Real Interference Depth of the Active Abrasive Grain

2020

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Distribution of the maximum undeformed chip thickness can be approximated as the reproduction of grooves and protrusions of the grinding surface. It plays a very important role in grinding process as it has a close influence on the prediction and modeling of grinding forces, tool life, and surface quality, as well as process stability. In this study, it is investigated from the perspective of the real interference depth of the active abrasive grain to cater to the performance evaluation of the grinding surface. Firstly, image processing techniques combined with three dimensional topography tests are utilized to extract grains' essential characteristics such as the protrusion height, shape, distribution and density. Then, grains' wear is quantified by the probability assignment function and Dempster-Shafer evidence theory. Based on this, the actual interference depth of a single grain is determined. Through grain's kinematics analysis and considering the effect of contact deformation on the actual contact arc length and affective cutting edge density, the distribution of chip thickness in the current grinding area is defined and its distribution model is established. Model's correctness and rationality are verified by grinding experiments of the slider raceway. Results demonstrate the grain's interference depth highly depends on its protrusion height, wear amount and grinding depth which is a primary contributor to the size of undeformed chip thickness, and grains' density, contact deformations mainly affect its distribution. The quantified distribution model of the maximum undeformed chip thickness lays a foundation for the topography modeling and integrity research of grinding surfaces. INDEX TERMS Abrasive particles wear, active cutting edges, grinding, image processing, interference depth, protrusion height, undeformed chip thickness.

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Performance Enhancement by Optimization of Poly Grain Size and Channel Thickness in a Vertical Channel 3-D NAND Flash Memory

Cited by 20 publications

References 15 publications

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories

Modeling of the Distribution of Undeformed Chip Thickness Based on the Real Interference Depth of the Active Abrasive Grain

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