2008
DOI: 10.1063/1.2991340
|View full text |Cite
|
Sign up to set email alerts
|

Performance enhancement of n-channel inversion type InxGa1−xAs metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer

Abstract: Articles you may be interested inImpact of Fermi level pinning inside conduction band on electron mobility in InGaAs metal-oxidesemiconductor field-effect transistors Possible unified model for the Hooge parameter in inversion-layer-channel metal-oxide-semiconductor fieldeffect transistors J. Appl. Phys. 113, 214508 (2013); 10.1063/1.4808465 GaN metal-oxide-semiconductor field-effect transistor inversion channel mobility modeling Inversion-type enhancement-mode Hf O 2 -based GaAs metal-oxide-semiconductor fiel… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

5
17
0

Year Published

2009
2009
2024
2024

Publication Types

Select...
5
5

Relationship

2
8

Authors

Journals

citations
Cited by 61 publications
(22 citation statements)
references
References 21 publications
5
17
0
Order By: Relevance
“…MOS transistors using these analogous InGaAs interfaces reveal much higher drive current and transconductance from the devices in which all detectable Ga 3+ were removed. 20 The extracted mobility further confirms the device performance increase via the removal of Ga 2 O 3 ͑Ref. 21͒.…”
supporting
confidence: 55%
“…MOS transistors using these analogous InGaAs interfaces reveal much higher drive current and transconductance from the devices in which all detectable Ga 3+ were removed. 20 The extracted mobility further confirms the device performance increase via the removal of Ga 2 O 3 ͑Ref. 21͒.…”
supporting
confidence: 55%
“…23 While Jiang et al 24 have shown that thin amorphous silicon interlayers can be successfully converted into ytterbium silicide, high temperature annealing could detrimentally impact on the interface quality as III-V materials are unstable at high temperature. 25 The Mg silicate formation procedure at 500°C outlined in this work may make it more suitable for silicon interlayer modification on III-V semiconductor substrates than other metal silicates.…”
Section: Resultsmentioning
confidence: 99%
“…Although much work has been carried out on III-V surface channel MOS field effect transistors (MOSFETs) with high-k dielectrics, a high defect density between the III-V semiconductor and the high-k gate dielectric is still a major issue. 1,2 Moving the channel away from the high-k dielectric in buried channel MOSFET structures with barrier layers have shown promising results. [3][4][5][6] Indium phospide (InP) is a promising barrier layer material as an excellent interface with the InGaAs channel can be obtained from in-situ growth of an InP barrier layer.…”
mentioning
confidence: 98%