Performance estimation and slack matching for pipelined asynchronous architectures with choice

Abstract

This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the problem of pipelining "slack matching." The approach targets systems with hierarchical topologies, which typically result when high-level (block structured) language specifications are compiled into data-driven circuit implementations. A significant contribution is that our approach is the first to efficiently handle architectures with choice (i.e., the presence of conditional computation constructs such if-then-else and conditional loops).The key idea behind the fast speed of our analysis method is to exploit information about the hierarchy of a given block-structured system, thereby yielding a runtime that is linear in the number of pipeline stages. In contrast, existing approaches typically represent an entire system as a single Petri net or marked graph, and then apply Markov chain analysis or other state enumeration methods with costly runtimes.Building upon our analysis approach, we introduce a novel solution to the problem of slack matching, i.e., determining optimal insertion of FIFO stages into a pipelined design to improve performance. We present both an optimal solution using an MILP formulation, and a fast heuristic algorithm that yielded optimal results for all of our examples.

De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits

“…Works by Gill et al [22] and Najibi et al [23] also address the existing non-deterministic behaviour through estimating the worst-case/upper bounds for the performance of these circuits. Simulation-based techniques have also been investigated [24][25] through iteratively tracing the signals in the circuit.…”

Removing concurrency for rapid functional verification

“…buffering) can be added to any channel without altering the behavior. This property has been found to hold for a wide variety of specifications, and to be very useful when building complex designs, as it can allow additional performanceenhancing buffers to be added late in the design without altering the correctness [24].…”

Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems

“…Canopy graph analysis has since been extended for analysis of more complex circuits, and the definition of the canopy graph itself has been extended and formalized in [7], [8].…”

“…As in past work [7], [8], we make this problem more tractable by focusing on a special class of asynchronous systems: those with hierarchically composed pipelined architectures. Such structures are quite common when the system is designed using high-level translation methods (e.g., Tangram/Haste [12], Balsa [6]) because high-level specification languages tend to be hierarchically block-structured.…”

“…This paper uses past performance analysis work [23], [10], [15], [7] as well as past work on bottleneck identification [8]. This section provides the necessary background on these approaches because they are used as a starting point for the work presented in this paper.…”