2011
DOI: 10.1016/j.simpat.2010.10.008
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Performance evaluation and design tradeoffs of on-chip interconnect architectures

Abstract: Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs. In this paper, a Network Calculusbased methodology is presented to analyze and evaluate the performance and cost metrics, such as latency and energy consumption. The 2D Mesh, Spide… Show more

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Cited by 22 publications
(11 citation statements)
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“…Analytical modeling is widely used in the evaluation of computer systems by researcher due to the significant speed-up offered by it [26,27], for example several analytical models [28][29][30] are presented for NoCs in recent years, and some of NoC analytical models are used from M/G/1 [31][32][33] The performance model presented in [34] uses a network calculus-based methodology for evaluating the performance metrics such as the load and the throughput, and a cost metric such as the energy consumption and the area overhead for all traffic patterns. Based on this method, the end-to-end delay and buffer size requirements are computed.…”
Section: Analytical Evaluation Of Dimbmentioning
confidence: 99%
“…Analytical modeling is widely used in the evaluation of computer systems by researcher due to the significant speed-up offered by it [26,27], for example several analytical models [28][29][30] are presented for NoCs in recent years, and some of NoC analytical models are used from M/G/1 [31][32][33] The performance model presented in [34] uses a network calculus-based methodology for evaluating the performance metrics such as the load and the throughput, and a cost metric such as the energy consumption and the area overhead for all traffic patterns. Based on this method, the end-to-end delay and buffer size requirements are computed.…”
Section: Analytical Evaluation Of Dimbmentioning
confidence: 99%
“…Recently, other topologies (e.g., FT, BFT, Spidergon, WK) has been adapted for SoC design [3,4,21,18]. However, there is no universal OCI, which can support all SoC application traffic patterns [9,14].…”
Section: Oci Customization Approachmentioning
confidence: 99%
“…It is able to model all traffic patterns with bounds defined by arrival curves. In this respect, designers can capture some dynamic features of the network based on shapes of the traffic flows [Bakhouya et al 2011]. Network calculus can also abstract many scheduling algorithms and arrival classes at single queue with multiplexed arrival flows, by service curves.…”
Section: Introductionmentioning
confidence: 99%