Performance Improvement of 1T DRAM by Raised Source and Drain Engineering

Ansari, Md. Hasan Raza; Cho, Seongjae

doi:10.1109/ted.2021.3056952

Cited by 22 publications

(12 citation statements)

References 48 publications

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“…Therefore, the scaling characteristics of the new structure have been improved. However, with the further scaling of the silicon column size in the future, the quantum effect will not be ignored [ 11 ]. Consequently, it is still necessary to explore other scaling methods, such as three-dimensional stacking, to simultaneously ensure the floating body volume and improve the storage density.…”

Section: Characteristics and Simulation Resultsmentioning

confidence: 99%

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

et al. 2022

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A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F2 cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM.

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Section: Characteristics and Simulation Resultsmentioning

confidence: 99%

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

et al. 2022

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“…In this work, the biasing and timing schemes are optimized to achieve STP, LTP, and LTD in the device and mimic the core-shell dual gate transistor as an electronic synapse. The working principle of the device as synapse is based on floating body effect and charge trapping and de-trapping from the nitride layer [ 15 , 16 , 17 , 32 , 33 ]. These operations are based on band-to-band-tunneling, impact ionization, hot carrier injection, and F–N tunneling in the device [ 15 , 16 , 17 , 19 , 32 , 33 ].…”

Section: Resultsmentioning

confidence: 99%

“…The working principle of the device as synapse is based on floating body effect and charge trapping and de-trapping from the nitride layer [ 15 , 16 , 17 , 32 , 33 ]. These operations are based on band-to-band-tunneling, impact ionization, hot carrier injection, and F–N tunneling in the device [ 15 , 16 , 17 , 19 , 32 , 33 ]. In this work, program operation is based on the BTBT mechanism due to its low power consumption and better reliability issue.…”

Section: Resultsmentioning

confidence: 99%

Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications

2021

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This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

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“…It is evident from the table that due to core-shell dual gate nanowire transistor achieves better retention time. The speed of the memory is estimated through write time (WT) and it is defined as the requirement of maximum time to perform the operation while current ratio (CR) is estimated through (I1/I0) [23], [28]. Core-gate helps to achieve deeper potential well compared to conventional double gate transistor, which enhance the retention of state "1" and thus, retention time of the memory [24], [30].…”

Section: Input Information Attentionmentioning

confidence: 99%

Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application

Ansari

Cho²,

Lee

et al. 2021

IEEE J. Electron Devices Soc.

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In this work, a synaptic device for neuromorphic system is proposed and designed to emulate the biological behaviors in the novel device structure of core-shell dual-gate (CSDG) nanowire flash memory. Floating-body effect in the device and charge trapping/de-trapping in the nitride layer are found to be effective for short-term potentiation (STP), long-term potentiation (LTP), and long-term depression (LTD), respectively. STP realizes a temporary potentiation in the artificial neural network, and it can transit to LTP through the process of rehearsal and meaningful association. The transition takes place at the 10 th pulse in a permissibly optimized CSDG synaptic device. The proposed device shows a stronger capacitive coupling between the dual gates, which forms a deeper potential well for charge storing and achieves better memory performance metrics such as sensing margin and retention time. The series of results reveal that the synaptic memory device is applicable to neuromorphic system due to the stronger gate controllability, multi-level weight adjustability, and Si processing compatibility.

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Performance Improvement of 1T DRAM by Raised Source and Drain Engineering

Cited by 22 publications

References 48 publications

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications

Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application

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