Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level

Patel, Jyoti; Sharma, Dheeraj; Yadav, Shivendra; Lemtur, Alemienla; Suman, Priyanka

doi:10.1016/j.mejo.2019.02.004

Cited by 54 publications

(18 citation statements)

References 27 publications

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“…TFET is essentially a reverse biased gated p-i-n diode [22][23][24]. Under negative ESD stress, ESD current is injected into the source terminal of TFET with drain terminal grounded.…”

Section: Basic Concept Of Electrostatic Discharge (Esd) Protection Tfetmentioning

confidence: 99%

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Wang

Mao

et al. 2021

Electronics

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Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

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“…TFET is essentially a reverse biased gated p-i-n diode [22][23][24]. Under negative ESD stress, ESD current is injected into the source terminal of TFET with drain terminal grounded.…”

Section: Basic Concept Of Electrostatic Discharge (Esd) Protection Tfetmentioning

confidence: 99%

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Wang

Mao

et al. 2021

Electronics

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“…Among several proposed TFETs, III-V TFETs appear more promising because of higher ON current [20][21][22]. In III-V TFETs, InAs homo-junction and GaSb-InAs hetero-junction TFETs exhibit superior performance [31,32].…”

Section: Device Descriptionmentioning

confidence: 99%

“…Among several post‐CMOS devices, TFETs have emerged as a promising device candidate for future low energy electronic circuit design [20, 21]. TFET with its band‐to‐band tunnelling mechanism achieves a high I ON / I OFF ratio and steep subthreshold swing (SS) (<60 mV/dec) at lower supply voltages [22, 23].…”

Section: Introductionmentioning

confidence: 99%

Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator

Japa

Majumder

Sahoo

et al. 2020

IET Circuits, Devices & Systems

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Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS-based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits significant p-in forward current with an increase in negative drain-to-source voltage bias. It is demonstrated that TFET transmission gate exhibits unconventional behaviour due to p-in forward current of the device. Leveraging this behaviour TFET RNG is designed that extracts random bits from delay variations of the TFET ring oscillator. The proposed TFET RNG achieves low area overhead when compared with the baseline CMOS designs. The proposed DPA countermeasure is demonstrated by integrating the original TFET substitution box (S-box) and TFET RNG. The proposed architecture is found to be resilient to DPA attack and the area overhead of single S-box and Advanced Encryption Standard AES is as low as 12 and 5%, respectively. Apart from low area overhead, the TFET designs with inherent device characteristics show high robustness against reverse engineering attacks which provide a higher level of security to TFET-based circuits and systems.

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“…The first stage is a simple differential amplifier and the second stage is a common source amplifier [39]. Typically, desirable characteristics of two‐stage op‐amp are large bandwidth, high input impedance, high gain, high common mode rejection ratio (CMRR), high slew rate, high speed and high power supply rejection ratio (PSRR) [40, 41]. The simulated characteristics of the two‐stage op‐amp are tabulated in Table 2 and its important characteristics such as gain and phase are shown in Fig.…”

Section: Circuit Implementationmentioning

confidence: 99%

Two‐stage op‐amp and integrator realisation through GaAsP/AlGaSb nanowire CP‐TFET

Lemtur

Sharma

Patel

et al. 2019

Micro & Nano Letters

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Tunnel field effect transistors (TFETs) have been extensively explored for the possibility of replacing metal oxide semiconductor FET (MOSFET) due to its steeper slope and for being more energy efficient. In this regard, device level performance of AlGaSb/GaAsP gate all around (Nanowire) charge plasma TFET (CP-TFET) shows promising results. To further verify these results, an overview of circuit performance is provided in this work, where analysis of two-stage operational amplifier (op-amp) is shown. Further, based on this op-amp, working of the integrator is also demonstrated. Simulations are carried out with the aid of Verilog A model in the Cadence environment. The outcome of circuit performance exhibits that the proposed device is viable for analogue applications and can be seriously considered for future low-power analogue designs.

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Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level

Cited by 54 publications

References 27 publications

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator

Two‐stage op‐amp and integrator realisation through GaAsP/AlGaSb nanowire CP‐TFET

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