Performance improvement of tall triple gate devices with strained SiN layers

Collaert, N.; Keersgieter, A. De; Anil, K.G.; Rooyackers, R.; Eneman, G.; Goodwin, M.J.; Eyckens, B.; Sleeckx, Erik; Marneffe, J.-F. de; Meyer, K. De; Absil, P.; Jurczak, M.; Biesemans, S.

doi:10.1109/led.2005.857692

Cited by 54 publications

(29 citation statements)

References 9 publications

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“…Successful results have been shown for digital device aspects by introducing uniaxial or biaxial strain in FinFET devices and confirm the expectation of device performance improvement [15,16]. This paper gives a comparison between the analog performance of standard and biaxially strained Si n-type triple-gate FinFETs with a SiO 2 -HfO 2 -TiN gate stack.…”

Section: Introductionsupporting

confidence: 69%

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Pavanello

Martino

Simoen

et al. 2008

Solid-State Electronics

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Section: Introductionsupporting

confidence: 69%

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Pavanello

Martino

Simoen

et al. 2008

Solid-State Electronics

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“…The total mobility enhancement total P w (Eq. [5]) is plotted versus transistor width in Figure 5 for gate-first (left) and gate-last (right) nFETs. For gate-first, CESL performs about 30% worse for narrow FinFETs than planar nFETs due to the low stress at the fin sidewall (Figure 3).…”

Section: Simulator Setupmentioning

confidence: 99%

“…To be competitive with planar FETs, FinFETs need to be combined with similar enhancement techniques as used on bulk silicon, such as stressors and gate-last integration schemes. Several groups have reported that stressors can significantly enhance FinFET mobility and performance (5)(6)(7). While for planar FETs, gate-last schemes (Replacement Metal Gate -RMG) have been shown to lead to further mobility enhancement when combined with stressors like Si 1-x Ge x and Si 1-y C y source/drains (8,9), relatively few reports exist on the combination of stressors and RMG on FinFETs to our knowledge.…”

Section: Introductionmentioning

confidence: 99%

(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

Eneman¹,

Witters²,

Collaert³

et al. 2012

ECS Trans.

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Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1 yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1 yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.

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“…ε c,zz < 0). Several fabrication techniques have been proposed to produce uniaxial strain in both planar MOSFETs and FinFETs, such as the employment of contact etch stop layers (CESL) [53][54][55] and of carbon or SiGe source-drain stressors [56][57][58]. Such techniques produce large stress components in the DCS, that in planar devices are typically aligned with the source-drain direction (see Fig.…”

Section: Determination Of the Strain And Stress Componentsmentioning

confidence: 99%

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

et al. 2009

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This paper reviews the basic methodologies and models used in the semi-classical modelling of CMOS transistors in the framework of the nowadays generalized scaling scenario. The capabilities to describe devices with arbitrary crystal orientations and strain configurations are discussed. Several simulation results are illustrated and compared to the experiments to assess the understanding of the underlying physics and the predictive capabilities of the models. A case study concerning the drain currents in nano-scale uniaxially strained MOSFETs is presented and it shows how the strain engineering may change the traditional on-current disadvantage of the p-MOS compared to the n-MOS transistors.

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Performance improvement of tall triple gate devices with strained SiN layers

Cited by 54 publications

References 9 publications

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

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