Performance Improvements of Random Dopant Fluctuation-Induced Variability in Negative Capacitance MOSFETS

Abstract

In this paper, we investigate the impact of random dopant fluctuation (RDF) on the statistical variations in negative capacitance MOSFETs (NCFETs) through a device simulation coupled with the Landau–Khalatnikov (LK) equation. Compact models for feedback mechanisms that are based on the internal gate voltage amplification in NCFETs are proposed. The results show that internal voltage amplification plays a decisive role in performance improvement of device variability. Further, our simulation study demonstrates that owing to the feedback mechanism, the dispersions of the performance parameters in NCFETs exhibit different statistical distribution characteristics compared to their MOSFET counterparts. Our study may provide further insight regarding device and/or circuit designs utilizing NCFETs.

Performance improvement of timing and power variations due to random dopant fluctuation in negative‐capacitance CMOS inverters

“…Because I ON in NCFETs is obviously higher than in the baseline MOSFETs, it is more significant to compare the relative standard deviation than the standard deviation. Therefore, NCFETs exhibit better immunity to RDF‐induced variability as compared to the baseline MOSFETs, because the RDF effect mainly affects the near‐threshold region, which means that the peak of standard deviation is close to V th [17]. Thus, NCFETs are verified to reduce the V th of the device, making it possible to scale V dd ; thus, the switch power dissipation is reduced.…”

“…Li et al [15] demonstrated that propagation delay is strongly dependent on FE damping constant, which is closely related to the FE response time. Furthermore, there also have been only a few reports concerning variability in NCFETs [16, 17] and NC‐FinFETs [18–21]. The research in [16] focused only on V th , I ON , and I OFF variations due to typical current–voltage characteristics in NCFETs with the possibility of negative differential resistance [22, 23] and negative drain induced barrier lowering (DIBL) phenomena [23].…”

Analog / Radio-Frequency Performance Analysis of Nanometer Negative Capacitance Fully Depleted Silicon-On-Insulator Transistors

“…To solve these problems, steep switching characteristics and lower operating voltage can be achieved by lowering the sub-threshold slope (SS). NCFETs based on ferroelectric on a gate stack have attracted significant attention in the field of advanced CMOS devices due to their lower SS (<60 mV/decade) [2]- [8]. Recently, NCFETs have proven to be suitable for a variety of low-power applications, such as wearables, bioelectronics, and the Internet of Things [9]- [12].…”