Performance optimization by wire and buffer sizing under the transmission line model

Abstract

As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-jiight delay of a line, it is necessay to consider the transmission line behavior for delay computation, We present in this paper an analytical formula for the delay Computation under the transmission line model. Extensive simulations with SPICE show the high fidelity ojthe formula. Compared with previous works [S, I I], our model leads to smaller average errors in delay estimation. Based on this formula, we show the propern, that the minimum delay for a transmission line with rejection occurs when the number of round trips is minimized (i.e., equals one). Besides, we show that the delay of a circuit path is a posynomial function in wire and buffer sizes, implving that a local optimum is equal to the global optimum. Thus, we can apply any ejicient search algorithm such as the well-known gradient search procedure to compute the globally optimal solution. Experimental results show that simultaneous wire and buffer sizing is venl effective for perjormance optimization under the transmission line model. 'tu;: the width of wire z. 2;: the length of wire z. Z,: the characteristic impedance of wire z. 21%: the propagation velocity of wire z. R,: the resistance of source. CL : the capacitance of load. VD D : the high voltage of power supply. K: the threshold voltage.( I ' , ~: the transmission coefficient at point i if a signal is transmitted from point z to point j.