Performance/Power Space Exploration for Binary64 Division Units

Nannarelli, Alberto

doi:10.1109/tc.2015.2448097

Cited by 14 publications

(3 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many nonrestoring algorithms have been designed and implemented, but the SRT algorithm is the most implemented approach. The basic SRT algorithm was implemented in 5,9,12,18,20,25,42,51,62,68,[76][77][78][79][80][81][82][83] for different applications utilizing different aspects of the algorithm. Figure 10 illustrates the comparative analysis regarding the hardware resource utilization of the USP-Awadhoot division algorithm-based divider and other SRT-based radix-n dividers.…”

Section: It Is the Simplest Parallel Computing Algorithmmentioning

confidence: 99%

Novel data dependent divider circuit block implementation for complex division and area critical applications

Patankar

Flores

Koel

2023

Sci Rep

View full text Add to dashboard Cite

This article elaborates on the state-of-the-art novel Udayan S. Patankar (USP)-Awadhoot algorithm for distinctive implementation area improvement for area-critical electronic applications. The proposed USP-Awadhoot divider is a digit recurrence class, but it can be flexibly implemented as a restoring or nonrestoring algorithm. The implementation example indicates the use of the Baudhayan-Pythagoras triplet method in association with the proposed USP-Awadhoot divider. The triplet method provides an easy way to generate Mat_Term1, Mat_Term2, and T_Term, which are further utilized with the proposed USP-Awadhoot divider. The USP-Awadhoot divider is implemented in three parts. First is preprocessing circuit stage for executing a dynamic separate scaling operation on input operands, ensuring the inputs are in the correct form. Second is the processing circuit stage for implementing the conversion logic expressed by the Awadhoot matrix, and third is the postprocessing circuit stage for recombining the individual results into the final result. The proposed divider works upto 285 MHz frequency with a power estimation of 3.366 W, also significantly improves the chip area requirements over those of the commercially and noncommercially implemented solutions.

show abstract

Section: It Is the Simplest Parallel Computing Algorithmmentioning

confidence: 99%

Novel data dependent divider circuit block implementation for complex division and area critical applications

Patankar

Flores

Koel

2023

Sci Rep

View full text Add to dashboard Cite

show abstract

“…Consider dividend bit count as 4n and divisor bit count as n. We can represent dividends in terms of partitions based on associated weights. Then we can represent the dividend as the addition of number partition as (61)(62)(63)(64).…”

Section: ) Smaller Dividend Division Algorithmmentioning

confidence: 99%

“…Many non-restoring algorithms were designed and implemented, but the SRT algorithm is the most implemented. The basic SRT algorithm was implemented in [7], [11], [17], [51], [57], [63], [64], [67], [69], [71], [32], [74], [76], [78], [81] for different applications utilizing different aspects of algorithm.…”

Section: Implementation Statisticsmentioning

confidence: 99%

Review of Basic Classes of Dividers Based on Division Algorithm

Patankar

Koel

2021

IEEE Access

View full text Add to dashboard Cite

The electronics world is very well described in two distinct but dependent interdisciplinary areas, namely hardware and software. Arithmetic operations are very vital building blocks of an electronic system. An algorithm is a systematic arrangement that helps develop a sophisticated electronic system, including hardware and software aspects. Addition, subtraction, multiplication, and division are critical elements of arithmetic implementation in the electronic system, but fewer efforts have been made to implement division than other arithmetic operations, even though the number of transistors on a chip is increasing beyond the Moore's law prediction. It is quite complicated to implement arithmetical operations; here, a sophisticated algorithm is essential to successful implementation. Technological upgrades are leading to a new paradigm of applications, where the performance of a division circuit or block is a vital and critical feature of a successful system. The lexicon of algorithms used in the implementation of the division operation in electronics systems is discussed in detail in the present article, which indicates the mathematical formulation, criticality, conversion pattern, hardware requirements, and logic used for conversion. The current report describes the broad classification of dividers into basic classes named digit recurrence, high radix, functional iteration, estimation, a look-up table, and variable latency. It also illustrates that, in practical implementation, many algorithms have been developed that combine one or many classes and are implemented with different hardware architectures. The study indicated the possibility of improving the presently available algorithms or creating a new algorithm to enhance practical implementation.

show abstract

High-Speed and Area-Efficient Modified Binary Divider

Pazhani¹,

Samuel²

2022

Circuits Syst Signal Process

View full text Add to dashboard Cite

Performance/Power Space Exploration for Binary64 Division Units

Cited by 14 publications

References 13 publications

Novel data dependent divider circuit block implementation for complex division and area critical applications

Novel data dependent divider circuit block implementation for complex division and area critical applications

Review of Basic Classes of Dividers Based on Division Algorithm

High-Speed and Area-Efficient Modified Binary Divider

Contact Info

Product

Resources

About