Performances analysis and evaluation of Xenomai with a H.264/AVC decoder

Kthiri, Moez; Kadionik, Patrice; Gal, Bertrand Le; Lévi, H.; Atitallah, Ahmed Ben

doi:10.1109/icm.2011.6177406

Cited by 3 publications

(2 citation statements)

References 2 publications

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“…From Table 7, we can conclude that our design has better performance than those in [27][28][29]. On the other hand, our design allows a high decrease in power consumption equal to 99% with almost the same performance compared to [30].…”

Section: Iq/it Streammentioning

confidence: 79%

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An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Atitallah¹,

Kammoun²,

Atitallah³

2020

Turk J Elec Eng & Comp Sci

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This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 × 4, 8 × 8, 16 × 16 , and 32 × 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standardcells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) enviro nment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

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Section: Iq/it Streammentioning

confidence: 79%

“…Power consumption Decoder video Specification (Watt) [27] CIF at 0.0625 -H.264/AVC PowerPC 440 at 400 MHz (INTER) (Linux/Xenomai) [28] 1080 p at 1.45 -HEVC ARM Cortex-A9 processor at (INTRA)…”

Section: Ref Fpsmentioning

confidence: 99%

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Atitallah¹,

Kammoun²,

Atitallah³

2020

Turk J Elec Eng & Comp Sci

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Programmable Auxiliary Co-Processing Unit for H.264 Decoder

Peesapati

Sabat

2019

2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)

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On Benchmarking of Real-time Mechanisms in Various Periodic Tasks for Real-time Embedded Linux

Koh

Choi²

2012

The Journal of Korea Robotics Society

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It is a real-time system that the system correctness depends not only on the correctness of the logical result of the computation but also on the result delivery time. Real-time Operating System (RTOS) is a software that manages the time of a microprocessor to ensure that the most important code runs first so that it is a good building block to design the real-time system. The real-time performance is achieved by using real-time mechanisms through data communication and synchronization of inter-task communication (ITC) between tasks. Therefore, test on the response time of real-time mechanisms is a good measure to predict the performance of real-time systems. This paper aims to analysis the response characteristics of real-time mechanisms in kernel space for real-time embedded Linux: RTAI and Xenomai. The performance evaluations of real-time mechanism depending on the changes of task periods are conducted. Test metrics are jitter of periodic tasks and response time of real-time mechanisms including semaphore, real-time FIFO, Mailbox and Message queue. The periodicity of tasks is relatively consistent for Xenomai but RTAI reveals smaller jitter as an average result. As for real-time mechanisms, semaphore and message transfer mechanism of Xenomai has a superior response to estimate deterministic real-time task execution. But real-time FIFO in RTAI shows faster response. The results are promising to estimate deterministic real-time task execution in implementing real-time systems using real-time embedded Linux.

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Performances analysis and evaluation of Xenomai with a H.264/AVC decoder

Cited by 3 publications

References 2 publications

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Programmable Auxiliary Co-Processing Unit for H.264 Decoder

On Benchmarking of Real-time Mechanisms in Various Periodic Tasks for Real-time Embedded Linux

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