Physical layout automation for system-on-packages

Ravichandran, Ramprasad; Minz, J.R.; Pathak, Mohit; Easwar, S.; Lim, Sung Kyu

doi:10.1109/ectc.2004.1319313

Cited by 10 publications

(3 citation statements)

References 34 publications

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“…So far, there are only a few publications on the physical design for 2.5D. These works are mostly focused on the cell placement for SoC [5] and not on the block placement [6]. The number of publications, which effectively apply mathematical models on 2.5D SiP needs [e.g.6], report the essential mathematical basics for 2.5D SiP integration, but target only one specific SiP technology at the very beginning of the physical design stage.…”

Section: Physical Design Flow For Sip Integrationmentioning

confidence: 99%

Integration technology parameters for physical design of vertical system-in-package

Polityko

Guttowski²,

Reichl³

2006

56th Electronic Components and Technology Conference 2006

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A promising solution for achieving highest integration density has been seen in vertical integration of heterogeneous components as a System-in-Package (SiP). An important success factor of 2.5/3D SiP is efficiency in physical design. The main content of this article is an introduction to the structuring of physical design, novel classification of 2.5D technologies, and the calculation of a parameter set, which provides key data for an objective comparison and selection of integration technologies for the design process of vertical integrated SiP.

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Section: Physical Design Flow For Sip Integrationmentioning

confidence: 99%

Integration technology parameters for physical design of vertical system-in-package

Polityko

Guttowski²,

Reichl³

2006

56th Electronic Components and Technology Conference 2006

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“…Some of the recent congestiondriven 2D circuit placement works include [8,9,10]. Recently, physical design algorithms for 3D System-On-Package designs have been proposed [11,12,13,14].…”

Section: Introductionmentioning

confidence: 99%

3D module placement for congestion and power noise reduction

Minz¹,

Lim

Koh

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this work, we propose a 3D module and decap (decoupling capacitance) placement algorithm that simultaneously reduces the power supply noise and wire congestion. We provide efficient algorithms for 3D power supply noise and congestion analysis to guide our 3D module placement process. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both decap amount and congestion with only small increase in area, wirelength, and runtime.

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“…Recent work on thermal-aware physical design algorithms include [4], [5], [6], [7], [8], [9]. Recently, physical design algorithms for 3D System-On-Package designs have been proposed including 3D placement [10], [11] and 3D routing [12], [13]. The remainder of this paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

Thermal and Crosstalk-Aware Physical Design for 3D System-On-Package

Minz¹,

Wong²,

Lim

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this article, we present the first physical layout algorithm for 3D SOP that performs thermal-aware 3D placement and crosstalkaware 3D global routing. Existing approaches consider thermal distribution and crosstalk issues as an afterthought, which may require expensive cooling scheme and additional routing layers. Our goal is to overcome this problem with our thermal and crosstalk-aware 3D layout tools. The traditional design objectives such as performance, area, wirelength, and via costs are considered simultaneously to ensure high quality results. Related experimental results demonstrate the effectiveness of our approach. 1 A special issue on SOP (vol. 27, issue 2, May 2004) provides a comprehensive survey of the state-of-the-art in SOP technology. SOC complete system on one chip MCM interconnects components SIP stacked chips or packages SOP optimizes btw chip/package

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Physical layout automation for system-on-packages

Abstract: System-On-Package (SOP)

Cited by 10 publications

References 34 publications

Integration technology parameters for physical design of vertical system-in-package

Integration technology parameters for physical design of vertical system-in-package

3D module placement for congestion and power noise reduction

Thermal and Crosstalk-Aware Physical Design for 3D System-On-Package

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