Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon-germanium heterojunctions

Abstract

Using graded silicon-germanium heterojunctions, the green tunnel field-effect transistor (TFET) can be scaled down into sub-10 nm regimes without short-channel effects. This work elucidates numerically the physical operation and device design of extremely short-channel TFETs with graded silicon-germanium heterojunctions for future low-power and high-performance applications. Critical device factors, such as the drain profile and bandgap engineering, were examined to generate favorable characteristics in the on-current, on-off switching, and off-leakage of very short TFETs. A mildly doped drain with a pure Ge source is preferred in designing the graded TFETs to optimize a desirable green transistor for low-power integrated circuits.

Drive current enhancement in tunnel field-effect transistors by graded heterojunction approach

“…Therefore, it is difficult to explain why the on-current lowering does not occur in SiGe-source n-type TFETs. 10,14 Additionally, previous publications 6,15 have shown that the on-current lowering in abrupt Si/SiGe p-type TFETs can be resolved by applying the graded heterojunction technique, but the physical reason still remains uncertainty. The current enhancement in graded p-type TFETs is simply attributed to the narrowed tunnel barriers.…”

Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications

“…Moreover, by designing a high-k spacer dielectric, we obtained an improved vertical tunneling current as well as a lower τ. The proposed device with L ch = 5 nm exhibited excellent characteristics, including an I on of 142 μA/μm, S of 29.1 mV/dec, I on /I off ratio of 1.27×10 7 , and τ of 0.58 ps. We confirmed that the proposed device is suitable for ultra LP devices at V DS of 0.2 V.…”

“…Recently, tunneling FETs (TFETs) have been considered as promising candidates for next-generation LP devices because TFETs that are based on band-to-band tunneling (BBT) operations can realize attractive advantages such as lower off-state current (I off ) and superior S [1][2][3][4][5]. However, as the channel length (L ch ) decreases below 10 nm, S and I off values of TFETs are degraded drastically because of the drain-induced barrier thinning (DIBT) phenomenon, as well as direct tunneling between the source and drain, which is caused by the SCE in TFETs [6,7]. Therefore, it is difficult for conventional TFETs with L ch values below 10 nm to obtain outstanding LP performance, and a novel structure and TFET operation principle is required to realize a sub-10 nm LP device.…”

Ge/Si Heterojunction Tunnel Field-Effect Transistors and Their Post Metallization Annealing Effect

“…Moreover, the larger bandgap of the Si channel and drain can suppress the leakage current in the drain of nTFETs. However, large lattice mismatch between Ge and Si makes formation of a Ge/Si heterojunction difficult [17] and, therefore, the experimental results of TFETs with the SiGe/Si heterojunction have been reported more than those of TFETs with a pure-Ge/Si heterojunction [18]- [20].…”