Physically Based Modeling of Stress-Induced Variation in Nanoscale Transistor Performance

Xu, Nuo; Wang, Lynn Tao-Ning; Neureuther, Andrew R.; Liu, Tsu‐Jae King

doi:10.1109/tdmr.2011.2144598

Cited by 13 publications

(9 citation statements)

References 15 publications

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“…One is to use average stress as an approximation [7]. The other is to use an analytical formula to approximate stress distribution [12], [13]. In this paper, both methods are used.…”

Section: B Development Of Stress Modelmentioning

confidence: 99%

“…Therefore, an analytical model suitable for SPICE simulation is needed. Related modeling works have been done by many researchers [7], [9]- [13], and these works can be divided into two classes. One is to directly relate layout parameters to device parameters such as mobility (μ) and threshold voltage (V th ) [9]- [11].…”

mentioning

confidence: 99%

“…Such modeling methods are based on data fitting and lack physical insight; the model developed for one technology may not be suitable for another. In comparison, the other calculates stress from layout parameters and then links the stress to device parameters through theoretical derivation [7], [12], [13]. Since such models reveal the physical insight, they can be applied to a wider range and are scalable for future process nodes.…”

mentioning

confidence: 99%

“…In the meantime, many models are focused on 1-D effect, i.e., only stress component and layout parameters along the longitudinal direction are considered [9]- [12]. However, more and more studies show that 1-D description is not enough [13], [14]. Stress from the transverse direction also has influence that cannot be neglected, and layout parameters along the transverse direction should also be taken into consideration.…”

mentioning

confidence: 99%

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A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

Tan

et al. 2012

IEEE Trans. Electron Devices

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Strain technology has become indispensable for present CMOS integrated circuits (ICs) as the feature size of transistor shrinks. In the meantime, stress-induced variation has also become an unavoidable problem. Unintentional stress, such as shallow trench isolation (STI)-induced stress, is one of the main variation sources and is strongly layout dependent. In this paper, a new 2-D layout-dependent STI stress model and related device parameter model are proposed. The stress model captures layout parameters along both the longitudinal direction and the transverse direction, based on which channel stress induced by STI is derived. Device parameters including threshold voltage, mobility, and saturation velocity are then modified according to several analytical models. The model can be integrated into standard CMOS IC design flow. By comparing with TCAD simulation and experiments with 65-nm process, it shows that the new model can give a better prediction accuracy than the original process design kit.

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“…One is to use average stress as an approximation [7]. The other is to use an analytical formula to approximate stress distribution [12], [13]. In this paper, both methods are used.…”

Section: B Development Of Stress Modelmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

Tan

et al. 2012

IEEE Trans. Electron Devices

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“…However, such a mechanical stress is not uniformly distributed on the channel plane, which results in a non-homogeneous channel plane conductive properties [1]. A pure electrical characterization technique for measuring the gate tunneling current I g only gives the average scalar value of the I g current at the gate contact, giving no information about the non-homogeneous space distributed conductive properties in nano-scaled MOSFET.…”

Section: Introductionmentioning

confidence: 99%

Experimental and Simulation Results of Magnetic Modulation of Gate Oxide Tunneling Current in Nanoscaled MOS Transistors

Rodriguez-Ruiz

Gutierrez-D

Sarmiento-Reyes

et al. 2015

IEEE Electron Device Lett.

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An experimental-simulation methodology to explore the spatially nonhomogeneous properties of the tunneling current in nanoscaled MOSFET is introduced. The magnetic field B is introduced into the Schrödinger-Poisson system, which allows simulating the effect of the B field on the gate oxide tunneling current and be compared with experimental data. We found out that sweeping the B field from negative to positive values is equivalent to scan or map the tunneling mechanism along the channel from source to drain. The proposed methodology is useful for studying nonhomogeneous space distributed conductive properties, and it was validated with a 28-nm n-type Si MOSFET.

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