Picowatt 0.5 V supply with 3 ppm/°C CMOS voltage reference for energy harvesting system

Liu, Jingfeng; Li, Quan; Liu, Xin; Li, Zhiqiang; Liu, Yu; Lin, Zhiting; Wu, Xiulong

doi:10.1587/elex.15.20180372

Cited by 4 publications

(1 citation statement)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Besides, the VR also needs to produce a stable voltage against process, supply voltage, and temperature (PVT) variations. Compared to the bandgap voltage reference (BGR) using BJTs and large resistors [1,2,3,4,5,6,7,8], the sub-threshold CMOS VRs (CVRs) are attractive alternatives for both low-voltage and low-power operation with less chip areas [9,10,11,12,13,14,15,16,17,18].…”

Section: Introductionmentioning

confidence: 99%

A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load

Yu,

Zhang,

2024

IEICE Electron. Express

View full text Add to dashboard Cite

This paper proposes a self-biased sub-threshold CMOS voltage reference for ultra-low-power application. In the current generation path, a source degeneration active load (SDAL) is added to reduce the variation of the reference current (IR) which helps to produce a stable voltage reference (VREF). Moreover, by utilizing the line sensitivity (LS) improving circuit, the dependence of VREF on the supply voltage (VDD) can be largely reduced. The proposed design is fabricated in a standard 0.18-µm CMOS process. 11-chip measurement results show the prototype design can provide an 147.1 mV average voltage with a minimum power consumption of 353 pW at 27 ℃. The line sensitivity (LS) is only 0.014%/V, while the power supply rejection ratio (PSRR) at 10 Hz is -68 dB. The average temperature coefficient (TC) is 72 ppm/°C from -20 °C to +80 °C, and the die area is only 0.0019 mm 2 .

show abstract

Section: Introductionmentioning

confidence: 99%

A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load

Yu,

Zhang,

2024

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

A Comprehensive Study of Different Techniques for Voltage References

Duggal

Pandey

Niranjan

2023

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.

show abstract

An Ultra-Low Power, Low Voltage, Low Line Sensitivity, High PSRR, Voltage Reference for IoT Applications

Duggal,

Pandey,

Niranjan

2024

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

This paper proposes an all MOSFET transistor-based voltage reference with ultra-low power consumption and high PSRR for Internet of Things applications. The reference voltage is computed using the gate source voltages of the five NMOS transistors, excluding the use of any transistors with high threshold voltages. To provide a steady clamping voltage for the current source, a supply voltage stability circuit with a current source is added which enhances the proposed voltage reference line sensitivity and PSRR. It has been designed and simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology to simulate the proposed voltage reference where all MOSFETs function in the subthreshold region with a 0.5[Formula: see text]V minimum supply voltage. The proposed voltage reference produces a reference voltage of 129.7[Formula: see text]mV with a supply voltage range of 0.5–3[Formula: see text]V. Based on simulation results, the proposed voltage reference has an active area of 0.001[Formula: see text]mm2, requires 11.2[Formula: see text]pW of power and has a line sensitivity of 0.021%/V. For a temperature range of [Formula: see text]40∘C to [Formula: see text]C, the circuit achieves a temperature coefficient of 38.2[Formula: see text]ppm/∘C. The power supply rejection ratio of the proposed voltage reference is [Formula: see text]101.5[Formula: see text]dB at 10[Formula: see text]Hz and [Formula: see text]90[Formula: see text]dB at 100[Formula: see text]Hz. The output noise at 100[Formula: see text]Hz and 1[Formula: see text]kHz is 4.68[Formula: see text]and 4.22[Formula: see text][Formula: see text]V/[Formula: see text]Hz, respectively.

show abstract

Picowatt 0.5 V supply with 3 ppm/°C CMOS voltage reference for energy harvesting system

Cited by 4 publications

References 9 publications

A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load

A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load

A Comprehensive Study of Different Techniques for Voltage References

An Ultra-Low Power, Low Voltage, Low Line Sensitivity, High PSRR, Voltage Reference for IoT Applications

Contact Info

Product

Resources

About