Pipelined execution of data-parallel algorithms

Gorev, Maksim; Ubar, Raimund

doi:10.1109/bec.2014.7320568

Cited by 1 publication

(2 citation statements)

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“…Architectu re Paradigm Goal [Shee et al, 2006] Multicore PP and MS Explores the parallelization of a JPEG application, using two paradigms, with heterogeneous components [Raeder et al, 2011] Cluster of PCs MS, DC and PP Proposes an analytical method to evaluate the best parallel programming paradigm for matrix multiplication [Gorev and Ubar, 2014] Multicore DLP and PP Combines paradigms, where it is preferable to use pipeline when data must be transferred several times [Aguilar and Leupers, 2015] MPSoC PP, DLP and TLP Proposes a tool that identifies multiple forms of parallelism from sequential embedded applications in a unified manner [Souza et al, 2017] MPPA-256…”

Section: Workmentioning

confidence: 99%

“…Table 1 presents the related works, architecture, and paradigms used, as well as the purpose of each one. Some works, such as [Shee et al, 2006] and [Gorev and Ubar, 2014], evaluate different paradigms in multicore processors. These architectures differ structurally from an MPSoC, integrating from 2 to 8 cores, enabling the use of shared memory and bus interconnection.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Investigating Parallel Programming Paradigms in HeMPS MPSoC Platform

Lopes¹,

Mello²,

Carvalho³

et al. 2019

Anais Do XX Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2019)

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This work investigates the use of parallel programming paradigms in the development of applications targeting a Multiprocessor System-on-Chip (MPSoC). We implemented Matrix Multiplication, Image Manipulation and Advanced Encryption Standard (AES) applications in the Master-Slave, Pipeline and Divide-and-Conquer paradigms, and applied execution time and power dissipation as criteria for evaluating the performance of the applications executing according to the paradigms on an MPSoC architecture. The obtained results allowed us to conclude that there are optimal application-paradigm relations. Pipeline presents lower execution time and lower power dissipation for the Image Manipulation application; whereas, Master-Slave performs better for the Matrix Multiplication and AES applications. However, when the input size of the applications increases, the Divide-and-Conquer paradigm tends to minimize the execution time for Matrix Multiplication application. The main contributions of this work are the development of applications, considering different paradigms, and the impact evaluation of these paradigms on MPSoC architecture.

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