Pipelined FFT for wireless communications supporting 128&amp;#x2013;2048 / 1536 -point transforms

Barahimi

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

2016

The Physical layer architectures for the next generation of wireless devices will be characterized by a high degree of flexibility for real-time adaptation to communication conditions variability. OFDM-based architectures are strong candidates for the Physical layer implementation in 5G systems and one of the most important baseband processing operations required by this waveform is the Fast Fourier Transform (FFT). This paper proposes a dynamically reconfigurable FFT processor supporting FFT sizes and throughputs required by the most widely used wireless standards. The FFT reconfiguration was achieved by means of FPGA-based Dynamic Partial Reconfiguration (DPR) techniques, which enables run-time FFT size adaptation according to communication requirements and better resource utilization. The impact of DPR in terms of reconfiguration time and power consumption overhead was evaluated. The obtained results encourage the exploitation of DPR techniques to implement reconfigurable hardware infrastructures for OFDM baseband processing engines.

Section: Methodsmentioning

confidence: 99%

Dynamically reconfigurable FFT processor for flexible OFDM baseband processing

Barahimi

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

2016

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

“…In [15], a serial input, serial output FFT pipeline is proposed which combines radix-2, and radix-3 computations and requires only (N − 1) memory elements for N -point transform. This architecture supports the FFT sizes in 3GPP LTE specification but misses the IFFT sizes.…”

Section: Existing Ifft/fft Architectures For Ofdm Systemmentioning

confidence: 99%

Efficient architecture mapping of FFT/IFFT for cognitive radio networks

Wang

Yin

Cho

et al. 2014

Self Cite

Cognitive radio networks require flexibility to support a variety of wireless communication system standards. Many modern systems utilize some form of orthogonal frequency division multiplexing (OFDM) and single-carrier frequencydivision multiple access (SC-FDMA) often augmented with multiple input multiple output (MIMO) antenna schemes. A common module in these standards is the fast Fourier transform (FFT) and its inverse. Although many architectures exist for traditional power-of-two FFT lengths, the recent 3GPP LTE standards define non-power-of-two transform lengths. The various FFT and IFFT lengths for both the uplink and downlink processing require support for radix-2, radix-3, and radix-5 modules. In this paper, we propose a highly flexible FFT/IFFT architecture that can support a broad variety of transform sizes and efficient mapping to programmable testbed platforms for cognitive radio networks. This novel architecture will provide a range of transform sizes of the general form (2 n 3 k 5 l ), and for use in emerging algorithms for massive MIMO detectors.Index Terms-Discrete Fourier transform, FFT/IFFT, 3GPP LTE/LTE-Advanced, VLSI architecture, pipelined architecture.

“…The operation parameters in each PE are the size of the feedback memory stream(s) (grey rectangles above the butterflies) and the set of twiddle factors (W N ) used to rotate the butterfly results. Details about the butterfly operations and internal structure can be found in [5,9]. The number of PEs of each type, as well as their location in the pipeline is defined by the factorizations from Table 1 and the chosen FFT algorithm.…”

Section: Fft Architecturementioning

confidence: 99%

Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications

Barahimi

Lecture Notes in Computer Science

2016

Cognitive Radios (CR) are viewed as a solution for spectrum utilization and management in next generation wireless networks. In order to adapt themselves to the actual communications environment, CR devices require highly flexible baseband processing engines. One of the most relevant operations involved in radio baseband processing is the FFT. This work presents a reconfigurable FFT processor supporting FFT sizes and throughputs required by the most used wireless communication standards. By employing Dynamic Partial Reconfiguration (DPR), the implemented design can adapt the FFT size at run-time and specialize its operation to the immediate communication demands. This translates to hardware savings, enhanced resource usage efficiency and possible power savings. The results obtained for reconfiguration times suggest that DPR techniques are a viable option for designing flexible and adaptable baseband processing components for CR devices.