Pipelined median architecture

Abstract

The core processing step of the noise reduction median filter technique is to find the median within a window of integers. A four-step procedure method to compute the running median of the last N W-bit stream of integers showing area and time benefits is proposed. The method slices integers into groups of B-bit using a pipeline of W/B blocks. From the method, an architecture is developed giving a designer the flexibility to exchange area gains for faster frequency of operation, or vice versa, by adjusting N, W and B parameter values. Gains in area of around 40%, or in frequency of operation of around 20%, are clearly observed by FPGA circuit implementations compared with latest methods in the literature.

Low‐latency median filter core for hardware implementation of 5 × 5 median filtering

“…In order to compare the proposed work with previous work, we have implemented on the same FPGA device the median calculation algorithm presented in [19]. We choose the implementing [19] method over [3], as it can compute the median in W/B steps, whereas [3] takes W steps for W-bit integers.…”

“…The presented LLMF core architecture takes 8-bit integers as input; however, the speed of the architecture would remain the same for higher than 8-bit also, such as 16-bit, 24-bit, and so on, as the proposed architecture involves word-level processing rather than bit-level processing presented in [3,19]. In word-level processing, all the bits of an integer (word) are processed in parallel.…”

“…In word-level processing, all the bits of an integer (word) are processed in parallel. The latency of the proposed architecture is also independent of bit-length (W) of integers, whereas with an increase in W, the latency in [3,19] will also increase, as they are W-step and W/B-step methods, respectively, where B is a design parameter having an integer value >1.…”

Fast median‐finding word comparator array

“…Median is the middle value in the sorted N = 9 integers of 3 × 3 sliding window, and median sorting has O(NlogN ) complexity [1]. Partial sorting techniques are evolving which significantly reduce computational complexity [2][3][4][5]. There are two methods for evaluating the median of a set of data, namely, sorting [4] and computing or non-sorting [2,3].…”

“…Circuit implementation on FPGA: The proposed architecture as well as the architecture in [6] are implemented on Xilinx FPGA Virtex 4 XC4VSX25. For the purpose of comparison with recently proposed methods [2,3,5], FPGA Virtex 4 XC4VSX25 is chosen with the specifications N = 9 and W = 8 bits ( Table 1). However the proposed method and [6] are specific to N = 9 unlike the other methods which can be extended to N = 25 and above.…”